AES/MASKED Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	72.945us	1	1	100.00
V1	smoke	aes_smoke	7.000s	247.698us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	13.000s	65.341us	5	5	100.00
V1	csr_rw	aes_csr_rw	11.000s	86.509us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	194.536us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	9.000s	653.830us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	65.090us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	11.000s	86.509us	20	20	100.00
		aes_csr_aliasing	9.000s	653.830us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	247.698us	50	50	100.00
		aes_config_error	11.000s	1.512ms	50	50	100.00
		aes_stress	13.000s	534.167us	50	50	100.00
V2	key_length	aes_smoke	7.000s	247.698us	50	50	100.00
		aes_config_error	11.000s	1.512ms	50	50	100.00
		aes_stress	13.000s	534.167us	50	50	100.00
V2	back2back	aes_stress	13.000s	534.167us	50	50	100.00
		aes_b2b	24.000s	423.804us	50	50	100.00
V2	backpressure	aes_stress	13.000s	534.167us	50	50	100.00
V2	multi_message	aes_smoke	7.000s	247.698us	50	50	100.00
		aes_config_error	11.000s	1.512ms	50	50	100.00
		aes_stress	13.000s	534.167us	50	50	100.00
		aes_alert_reset	7.000s	520.133us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	295.365us	50	50	100.00
		aes_config_error	11.000s	1.512ms	50	50	100.00
		aes_alert_reset	7.000s	520.133us	50	50	100.00
V2	trigger_clear_test	aes_clear	13.000s	876.594us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	695.292us	1	1	100.00
V2	reset_recovery	aes_alert_reset	7.000s	520.133us	50	50	100.00
V2	stress	aes_stress	13.000s	534.167us	50	50	100.00
V2	sideload	aes_stress	13.000s	534.167us	50	50	100.00
		aes_sideload	15.000s	531.832us	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	1.127ms	50	50	100.00
V2	stress_all	aes_stress_all	1.750m	53.545ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	55.741us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	26.000s	94.898us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	26.000s	94.898us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	13.000s	65.341us	5	5	100.00
		aes_csr_rw	11.000s	86.509us	20	20	100.00
		aes_csr_aliasing	9.000s	653.830us	5	5	100.00
		aes_same_csr_outstanding	4.000s	76.508us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	13.000s	65.341us	5	5	100.00
		aes_csr_rw	11.000s	86.509us	20	20	100.00
		aes_csr_aliasing	9.000s	653.830us	5	5	100.00
		aes_same_csr_outstanding	4.000s	76.508us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	2.517m	8.156ms	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	665.067us	49	50	98.00
		aes_control_fi	1.000m	10.005ms	284	300	94.67
		aes_cipher_fi	32.000s	10.019ms	341	350	97.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	19.000s	97.245us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	19.000s	97.245us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	19.000s	97.245us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	19.000s	97.245us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	13.000s	123.717us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	824.833us	5	5	100.00
		aes_tl_intg_err	27.000s	125.995us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	27.000s	125.995us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	7.000s	520.133us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	19.000s	97.245us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	247.698us	50	50	100.00
		aes_stress	13.000s	534.167us	50	50	100.00
		aes_alert_reset	7.000s	520.133us	50	50	100.00
		aes_core_fi	2.400m	10.022ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	19.000s	97.245us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	88.589us	50	50	100.00
		aes_stress	13.000s	534.167us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	13.000s	534.167us	50	50	100.00
		aes_sideload	15.000s	531.832us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	88.589us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	88.589us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	88.589us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	88.589us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	88.589us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	13.000s	534.167us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	13.000s	534.167us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	665.067us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	665.067us	49	50	98.00
		aes_control_fi	1.000m	10.005ms	284	300	94.67
		aes_cipher_fi	32.000s	10.019ms	341	350	97.43
		aes_ctr_fi	3.000s	67.634us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	665.067us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	665.067us	49	50	98.00
		aes_control_fi	1.000m	10.005ms	284	300	94.67
		aes_cipher_fi	32.000s	10.019ms	341	350	97.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	32.000s	10.019ms	341	350	97.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	665.067us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	665.067us	49	50	98.00
		aes_control_fi	1.000m	10.005ms	284	300	94.67
		aes_ctr_fi	3.000s	67.634us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	665.067us	49	50	98.00
		aes_control_fi	1.000m	10.005ms	284	300	94.67
		aes_cipher_fi	32.000s	10.019ms	341	350	97.43
		aes_ctr_fi	3.000s	67.634us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	7.000s	520.133us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	665.067us	49	50	98.00
		aes_control_fi	1.000m	10.005ms	284	300	94.67
		aes_cipher_fi	32.000s	10.019ms	341	350	97.43
		aes_ctr_fi	3.000s	67.634us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	665.067us	49	50	98.00
		aes_control_fi	1.000m	10.005ms	284	300	94.67
		aes_cipher_fi	32.000s	10.019ms	341	350	97.43
		aes_ctr_fi	3.000s	67.634us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	665.067us	49	50	98.00
		aes_control_fi	1.000m	10.005ms	284	300	94.67
		aes_ctr_fi	3.000s	67.634us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	665.067us	49	50	98.00
		aes_control_fi	1.000m	10.005ms	284	300	94.67
		aes_cipher_fi	32.000s	10.019ms	341	350	97.43
V2S		TOTAL			956	985	97.06
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	48.000s	2.015ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			1564	1602	97.63

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.38	98.64	96.54	99.45	95.37	97.99	100.00	98.36	98.39

Failure Buckets

Job timed out after * minutes has 13 failures:
- Test aes_control_fi has 11 failures.
  - 10.aes_control_fi.88112217135836741998274016627364943382900237480231666216109376478085928707071
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 32.aes_control_fi.12734819563463473739237680472863936949539469769126003319415921580250138742705
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/32.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 2 failures.
  - 130.aes_cipher_fi.51990780783495621592301150542941157083119387418121765119994959212554163916002
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/130.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 328.aes_cipher_fi.87655210167499046219751938633415637005289095344829545921591927813008181221062
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/328.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.68019392384390663332319135301299178976739085727118883064290993522855044901201
Line 894, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 847724356 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 847724356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.19692944961632617468548677977054451821473759743275204656715168041832874354553
Line 442, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2516652921 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2516652921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 47.aes_cipher_fi.31843564169222513206521997867601984425727087714077151137431122571635022205790
    Line 146, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/47.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013173455 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013173455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 55.aes_cipher_fi.105779752290648164980242332737862853904790641443460215787508648397898461143188
    Line 142, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/55.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010263571 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010263571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 35.aes_control_fi.88584014841606994274911880789670736716722448639767972582344071653583199346911
    Line 132, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008878911 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008878911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 83.aes_control_fi.26713624384872268141396514497566355845385909755309232859211769899958108619017
    Line 138, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/83.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010023316 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010023316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 2.aes_core_fi.81439042637755536000568662378520917301185296138255499620948748934552942767022
    Line 141, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014072613 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014072613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 15.aes_core_fi.35447854607697066789458357456135423428164921302316511313326786941396097086330
    Line 132, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007353181 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007353181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.63426504234696978171979210495337059132389740150637027385552681446391573147709
    Line 330, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 489075983 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 489075983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.46085505952250177705235833338498828118028879079146837946961847153022530076521
    Line 159, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 208492063 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 208492063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 37.aes_fi.103049856362179845059557273969974470556330887669018382468834578389155286995408
    Line 19473, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/37.aes_fi/latest/run.log
```
  UVM_FATAL @  45330817 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  45330817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 47.aes_core_fi.41082965481464996426809836120682584647705321009999817156454383317463946592955
    Line 133, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/47.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021825334 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xcb6e7184, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10021825334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```