AES/UNMASKED Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	77.688us	1	1	100.00
V1	smoke	aes_smoke	3.000s	107.777us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	60.592us	5	5	100.00
V1	csr_rw	aes_csr_rw	2.000s	64.558us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	7.000s	186.706us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	363.320us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	81.598us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	64.558us	20	20	100.00
		aes_csr_aliasing	3.000s	363.320us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	3.000s	107.777us	50	50	100.00
		aes_config_error	3.000s	119.594us	50	50	100.00
		aes_stress	4.000s	100.958us	50	50	100.00
V2	key_length	aes_smoke	3.000s	107.777us	50	50	100.00
		aes_config_error	3.000s	119.594us	50	50	100.00
		aes_stress	4.000s	100.958us	50	50	100.00
V2	back2back	aes_stress	4.000s	100.958us	50	50	100.00
		aes_b2b	7.000s	557.175us	50	50	100.00
V2	backpressure	aes_stress	4.000s	100.958us	50	50	100.00
V2	multi_message	aes_smoke	3.000s	107.777us	50	50	100.00
		aes_config_error	3.000s	119.594us	50	50	100.00
		aes_stress	4.000s	100.958us	50	50	100.00
		aes_alert_reset	4.000s	133.364us	50	50	100.00
V2	failure_test	aes_man_cfg_err	3.000s	199.423us	50	50	100.00
		aes_config_error	3.000s	119.594us	50	50	100.00
		aes_alert_reset	4.000s	133.364us	50	50	100.00
V2	trigger_clear_test	aes_clear	4.000s	296.345us	49	50	98.00
V2	nist_test_vectors	aes_nist_vectors	4.000s	112.393us	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.000s	133.364us	50	50	100.00
V2	stress	aes_stress	4.000s	100.958us	50	50	100.00
V2	sideload	aes_stress	4.000s	100.958us	50	50	100.00
		aes_sideload	3.000s	138.540us	50	50	100.00
V2	deinitialization	aes_deinit	4.000s	140.367us	50	50	100.00
V2	stress_all	aes_stress_all	22.000s	7.313ms	10	10	100.00
V2	alert_test	aes_alert_test	2.000s	83.719us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	3.000s	101.847us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	3.000s	101.847us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	60.592us	5	5	100.00
		aes_csr_rw	2.000s	64.558us	20	20	100.00
		aes_csr_aliasing	3.000s	363.320us	5	5	100.00
		aes_same_csr_outstanding	3.000s	137.048us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	60.592us	5	5	100.00
		aes_csr_rw	2.000s	64.558us	20	20	100.00
		aes_csr_aliasing	3.000s	363.320us	5	5	100.00
		aes_same_csr_outstanding	3.000s	137.048us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	4.000s	158.412us	50	50	100.00
V2S	fault_inject	aes_fi	3.000s	76.021us	49	50	98.00
		aes_control_fi	41.000s	10.029ms	274	300	91.33
		aes_cipher_fi	43.000s	10.002ms	313	350	89.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	163.831us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	163.831us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	163.831us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	163.831us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.000s	257.142us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	3.558ms	5	5	100.00
		aes_tl_intg_err	4.000s	321.532us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	321.532us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	133.364us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	163.831us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	3.000s	107.777us	50	50	100.00
		aes_stress	4.000s	100.958us	50	50	100.00
		aes_alert_reset	4.000s	133.364us	50	50	100.00
		aes_core_fi	3.133m	10.019ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	163.831us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	59.956us	50	50	100.00
		aes_stress	4.000s	100.958us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	100.958us	50	50	100.00
		aes_sideload	3.000s	138.540us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	59.956us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	59.956us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	59.956us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	59.956us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	59.956us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	100.958us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	100.958us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.000s	76.021us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.000s	76.021us	49	50	98.00
		aes_control_fi	41.000s	10.029ms	274	300	91.33
		aes_cipher_fi	43.000s	10.002ms	313	350	89.43
		aes_ctr_fi	3.000s	109.084us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.000s	76.021us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.000s	76.021us	49	50	98.00
		aes_control_fi	41.000s	10.029ms	274	300	91.33
		aes_cipher_fi	43.000s	10.002ms	313	350	89.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	43.000s	10.002ms	313	350	89.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.000s	76.021us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.000s	76.021us	49	50	98.00
		aes_control_fi	41.000s	10.029ms	274	300	91.33
		aes_ctr_fi	3.000s	109.084us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.000s	76.021us	49	50	98.00
		aes_control_fi	41.000s	10.029ms	274	300	91.33
		aes_cipher_fi	43.000s	10.002ms	313	350	89.43
		aes_ctr_fi	3.000s	109.084us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	133.364us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.000s	76.021us	49	50	98.00
		aes_control_fi	41.000s	10.029ms	274	300	91.33
		aes_cipher_fi	43.000s	10.002ms	313	350	89.43
		aes_ctr_fi	3.000s	109.084us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.000s	76.021us	49	50	98.00
		aes_control_fi	41.000s	10.029ms	274	300	91.33
		aes_cipher_fi	43.000s	10.002ms	313	350	89.43
		aes_ctr_fi	3.000s	109.084us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.000s	76.021us	49	50	98.00
		aes_control_fi	41.000s	10.029ms	274	300	91.33
		aes_ctr_fi	3.000s	109.084us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.000s	76.021us	49	50	98.00
		aes_control_fi	41.000s	10.029ms	274	300	91.33
		aes_cipher_fi	43.000s	10.002ms	313	350	89.43
V2S		TOTAL			915	985	92.89
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	24.000s	672.062us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1521	1602	94.94

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.21	97.66	94.71	98.78	93.09	98.07	91.85	98.08	97.99

Failure Buckets

Job timed out after * minutes has 35 failures:
- Test aes_control_fi has 17 failures.
  - 7.aes_control_fi.110420549044958556900609121464719698023939432457819727864981825906916286308866
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 25.aes_control_fi.51392422759084580241580878072667113784658931221880111573275061391937399712649
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 15 more failures.
- Test aes_cipher_fi has 18 failures.
  - 72.aes_cipher_fi.108516920767265972565146484253254216854324291149502458662646036467455418979673
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/72.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 96.aes_cipher_fi.112457629408301302648741904315151390740247816718245612666938683291379006793000
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/96.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 16 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 19 failures:
- Test aes_cipher_fi has 19 failures.
  - 6.aes_cipher_fi.100784349031468480405223686543437588651163736329166151795394525705040382132942
    Line 133, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005557509 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005557509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 17.aes_cipher_fi.6705966889719302079892192303946624155158598099960269848039350535737606902390
    Line 142, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/17.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014363069 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014363069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 5.aes_control_fi.4111192927997441112708627548979343740164327128500776296591355747116088800728
    Line 138, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011896044 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011896044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 15.aes_control_fi.112909697106270639979977202900315498491648130232698825497664790843249732213298
    Line 142, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10029866658 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10029866658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

1.aes_stress_all_with_rand_reset.46297359831617829198459216342292505159924434948993502631792811906334806460657
Line 531, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1803700297 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1803700297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.51381444762622514658487728637948274336540605411112444040658161698471344674765
Line 441, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1883959950 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1883959950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 28.aes_core_fi.82163973823879968307047790512141987314362080147855356822234354142656601688950
    Line 146, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/28.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10032233737 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10032233737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 31.aes_core_fi.86408775617430908773303962153110955853019366724905402063394942613618362577764
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/31.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006551130 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006551130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 0.aes_stress_all_with_rand_reset.8953701536956543956919731576326033939472380900512722820067882776967758217049
    Line 161, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  15617475 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  15617475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.aes_stress_all_with_rand_reset.81345509298517789182668085325161946243202759311359922097828313594287471341269
    Line 136, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  93340777 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  93340777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.75298564326419265948885271659516809832608766061896651805140643120625253746667
    Line 183, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 156257646 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 156257646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:611) scoreboard [scoreboard] # * has 1 failures:
- Test aes_clear has 1 failures.
  - 12.aes_clear.51030408204553510281548925240178607873668103439846060396271245917796910291725
    Line 1805, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/12.aes_clear/latest/run.log
```
  UVM_FATAL @  45654208 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
           TEST FAILED MESSAGES DID NOT MATCH

                 0 5a 	 65 	 63 	 0
                 1 24 	 92 	 62 	 0
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

49.aes_fi.82526288763057577516758752123739244334602865150971883879391156995935144735366
Line 2969, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/49.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 56475097 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 56408430 PS)
  UVM_ERROR @  56475097 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  56475097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 61.aes_core_fi.19911121117022997817244165275268012354324322544230465579634401484064834159529
    Line 141, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/61.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019360382 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xc93fc184, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
  UVM_INFO @ 10019360382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```