CSRNG Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	139.054us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	34.305us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	101.242us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	48.000s	4.694ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	6.000s	67.369us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	251.104us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	101.242us	20	20	100.00
		csrng_csr_aliasing	6.000s	67.369us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	24.000s	1.348ms	200	200	100.00
V2	alerts	csrng_alert	51.000s	4.337ms	500	500	100.00
V2	err	csrng_err	4.000s	98.250us	491	500	98.20
V2	cmds	csrng_cmds	7.700m	46.352ms	50	50	100.00
V2	life cycle	csrng_cmds	7.700m	46.352ms	50	50	100.00
V2	stress_all	csrng_stress_all	32.600m	170.711ms	47	50	94.00
V2	intr_test	csrng_intr_test	3.000s	166.892us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	177.179us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	10.000s	429.936us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	10.000s	429.936us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	34.305us	5	5	100.00
		csrng_csr_rw	4.000s	101.242us	20	20	100.00
		csrng_csr_aliasing	6.000s	67.369us	5	5	100.00
		csrng_same_csr_outstanding	4.000s	202.909us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	34.305us	5	5	100.00
		csrng_csr_rw	4.000s	101.242us	20	20	100.00
		csrng_csr_aliasing	6.000s	67.369us	5	5	100.00
		csrng_same_csr_outstanding	4.000s	202.909us	20	20	100.00
V2		TOTAL			1428	1440	99.17
V2S	tl_intg_err	csrng_sec_cm	8.000s	305.010us	5	5	100.00
		csrng_tl_intg_err	11.000s	952.246us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	92.530us	50	50	100.00
		csrng_csr_rw	4.000s	101.242us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	51.000s	4.337ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	32.600m	170.711ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	24.000s	1.348ms	200	200	100.00
		csrng_err	4.000s	98.250us	491	500	98.20
		csrng_sec_cm	8.000s	305.010us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	24.000s	1.348ms	200	200	100.00
		csrng_err	4.000s	98.250us	491	500	98.20
		csrng_sec_cm	8.000s	305.010us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	24.000s	1.348ms	200	200	100.00
		csrng_err	4.000s	98.250us	491	500	98.20
		csrng_sec_cm	8.000s	305.010us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	24.000s	1.348ms	200	200	100.00
		csrng_err	4.000s	98.250us	491	500	98.20
		csrng_sec_cm	8.000s	305.010us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	24.000s	1.348ms	200	200	100.00
		csrng_err	4.000s	98.250us	491	500	98.20
		csrng_sec_cm	8.000s	305.010us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	24.000s	1.348ms	200	200	100.00
		csrng_err	4.000s	98.250us	491	500	98.20
		csrng_sec_cm	8.000s	305.010us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	24.000s	1.348ms	200	200	100.00
		csrng_err	4.000s	98.250us	491	500	98.20
		csrng_sec_cm	8.000s	305.010us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	51.000s	4.337ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	24.000s	1.348ms	200	200	100.00
		csrng_err	4.000s	98.250us	491	500	98.20
V2S	sec_cm_constants_lc_gated	csrng_stress_all	32.600m	170.711ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	51.000s	4.337ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	11.000s	952.246us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	24.000s	1.348ms	200	200	100.00
		csrng_err	4.000s	98.250us	491	500	98.20
		csrng_sec_cm	8.000s	305.010us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	24.000s	1.348ms	200	200	100.00
		csrng_err	4.000s	98.250us	491	500	98.20
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	24.000s	1.348ms	200	200	100.00
		csrng_err	4.000s	98.250us	491	500	98.20
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	24.000s	1.348ms	200	200	100.00
		csrng_err	4.000s	98.250us	491	500	98.20
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	24.000s	1.348ms	200	200	100.00
		csrng_err	4.000s	98.250us	491	500	98.20
		csrng_sec_cm	8.000s	305.010us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	24.000s	1.348ms	200	200	100.00
		csrng_err	4.000s	98.250us	491	500	98.20
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	5.850m	29.795ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1618	1630	99.26

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.59	98.53	96.37	99.91	97.14	92.08	100.00	95.61	90.15

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed has 9 failures:
  • Test csrng_err has 9 failures.

    • 42.csrng_err.53362759476985225797252830592413778657467093133424264905299921095916751722579
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/42.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 5600362 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @   5600362 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   5600362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 213.csrng_err.11318954948606147071576296807842874350329244937067727402869651496387050310037
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/213.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 2773029 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @   2773029 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   2773029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
  • Test csrng_stress_all has 3 failures.

    • 11.csrng_stress_all.111921240525810122430370458955564676712124224923401147271920160732560553004238
      Line 157, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/11.csrng_stress_all/latest/run.log

        UVM_ERROR @ 2510375288 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 2510375288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 24.csrng_stress_all.80216609908665030748777298978355682276350955564915434620036366006264708994560
      Line 148, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/24.csrng_stress_all/latest/run.log

        UVM_ERROR @ 9716119969 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 9716119969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.