EDN Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.430s 18.261us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.160s 57.107us 5 5 100.00
V1 csr_rw edn_csr_rw 1.230s 12.268us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.890s 873.421us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.790s 42.297us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.710s 53.228us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.230s 12.268us 20 20 100.00
edn_csr_aliasing 1.790s 42.297us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.753m 8.785ms 300 300 100.00
V2 csrng_commands edn_genbits 1.753m 8.785ms 300 300 100.00
V2 genbits edn_genbits 1.753m 8.785ms 300 300 100.00
V2 interrupts edn_intr 1.510s 21.482us 50 50 100.00
V2 alerts edn_alert 1.760s 50.986us 200 200 100.00
V2 errs edn_err 1.680s 37.475us 100 100 100.00
V2 disable edn_disable 1.330s 22.103us 50 50 100.00
edn_disable_auto_req_mode 1.780s 41.769us 50 50 100.00
V2 stress_all edn_stress_all 5.910s 592.920us 50 50 100.00
V2 intr_test edn_intr_test 1.210s 14.663us 50 50 100.00
V2 alert_test edn_alert_test 1.650s 39.613us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.440s 319.027us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.440s 319.027us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.160s 57.107us 5 5 100.00
edn_csr_rw 1.230s 12.268us 20 20 100.00
edn_csr_aliasing 1.790s 42.297us 5 5 100.00
edn_same_csr_outstanding 1.650s 78.526us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.160s 57.107us 5 5 100.00
edn_csr_rw 1.230s 12.268us 20 20 100.00
edn_csr_aliasing 1.790s 42.297us 5 5 100.00
edn_same_csr_outstanding 1.650s 78.526us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 7.970s 591.904us 5 5 100.00
edn_tl_intg_err 3.810s 301.850us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.340s 29.713us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.760s 50.986us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.970s 591.904us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.970s 591.904us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.970s 591.904us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.970s 591.904us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.760s 50.986us 200 200 100.00
edn_sec_cm 7.970s 591.904us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.760s 50.986us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.810s 301.850us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.703m 15.744ms 30 50 60.00
V3 TOTAL 30 50 60.00
TOTAL 1110 1130 98.23

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.83 98.87 94.29 91.35 92.44 96.33 97.56 92.94

Failure Buckets