ENTROPY_SRC/RNG_4BITS Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 3.000s 44.576us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 32.000s 67.769us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 6.000s 103.421us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 16.000s 2.490ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 534.055us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 3.000s 65.876us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 6.000s 103.421us 20 20 100.00
entropy_src_csr_aliasing 8.000s 534.055us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 3.000s 44.576us 50 50 100.00
entropy_src_rng 8.967m 19.024ms 300 300 100.00
entropy_src_fw_ov 9.883m 19.063ms 295 300 98.33
V2 firmware_mode entropy_src_fw_ov 9.883m 19.063ms 295 300 98.33
V2 rng_mode entropy_src_rng 8.967m 19.024ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 14.200m 20.041ms 397 400 99.25
V2 health_checks entropy_src_rng 8.967m 19.024ms 300 300 100.00
V2 conditioning entropy_src_rng 8.967m 19.024ms 300 300 100.00
V2 interrupts entropy_src_rng 8.967m 19.024ms 300 300 100.00
entropy_src_intr 34.000s 506.280us 50 50 100.00
V2 alerts entropy_src_rng 8.967m 19.024ms 300 300 100.00
entropy_src_functional_alerts 7.000s 176.505us 50 50 100.00
V2 stress_all entropy_src_stress_all 9.067m 19.260ms 49 50 98.00
V2 functional_errors entropy_src_functional_errors 6.133m 10.012ms 988 1000 98.80
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 22.000s 326.953us 50 50 100.00
V2 intr_test entropy_src_intr_test 32.000s 64.991us 50 50 100.00
V2 alert_test entropy_src_alert_test 3.000s 131.774us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 33.000s 140.577us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 33.000s 140.577us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 32.000s 67.769us 5 5 100.00
entropy_src_csr_rw 6.000s 103.421us 20 20 100.00
entropy_src_csr_aliasing 8.000s 534.055us 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 74.260us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 32.000s 67.769us 5 5 100.00
entropy_src_csr_rw 6.000s 103.421us 20 20 100.00
entropy_src_csr_aliasing 8.000s 534.055us 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 74.260us 20 20 100.00
V2 TOTAL 2319 2340 99.10
V2S tl_intg_err entropy_src_sec_cm 3.000s 101.533us 5 5 100.00
entropy_src_tl_intg_err 33.000s 239.178us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 8.967m 19.024ms 300 300 100.00
entropy_src_cfg_regwen 3.000s 15.593us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 8.967m 19.024ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 8.967m 19.024ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 8.967m 19.024ms 300 300 100.00
entropy_src_fw_ov 9.883m 19.063ms 295 300 98.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 6.133m 10.012ms 988 1000 98.80
entropy_src_sec_cm 3.000s 101.533us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 6.133m 10.012ms 988 1000 98.80
entropy_src_sec_cm 3.000s 101.533us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 8.967m 19.024ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 6.133m 10.012ms 988 1000 98.80
entropy_src_sec_cm 3.000s 101.533us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 6.133m 10.012ms 988 1000 98.80
entropy_src_sec_cm 3.000s 101.533us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 6.133m 10.012ms 988 1000 98.80
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 7.000s 176.505us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 33.000s 239.178us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 7.867m 20.039ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 2549 2570 99.18

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
94.08 97.36 93.25 98.34 95.12 79.76 96.88 89.27 95.98

Failure Buckets