HMAC Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	13.260s	1.821ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.040s	19.450us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.030s	106.280us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	11.370s	1.402ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.130s	3.359ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	15.073m	111.792ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.030s	106.280us	20	20	100.00
		hmac_csr_aliasing	6.130s	3.359ms	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.386m	4.557ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	2.059m	3.571ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.455m	8.221ms	30	30	100.00
		hmac_test_sha384_vectors	8.819m	13.598ms	75	75	100.00
		hmac_test_sha512_vectors	8.871m	27.312ms	75	75	100.00
		hmac_test_hmac256_vectors	15.980s	4.625ms	50	50	100.00
		hmac_test_hmac384_vectors	17.020s	380.211us	60	60	100.00
		hmac_test_hmac512_vectors	18.810s	416.167us	75	75	100.00
V2	burst_wr	hmac_burst_wr	42.930s	6.757ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	23.038m	30.782ms	10	10	100.00
V2	error	hmac_error	1.527m	1.666ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	2.259m	44.537ms	10	10	100.00
V2	save_and_restore	hmac_smoke	13.260s	1.821ms	10	10	100.00
		hmac_long_msg	1.386m	4.557ms	10	10	100.00
		hmac_back_pressure	2.059m	3.571ms	25	25	100.00
		hmac_datapath_stress	23.038m	30.782ms	10	10	100.00
		hmac_burst_wr	42.930s	6.757ms	50	50	100.00
		hmac_stress_all	43.062m	289.437ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	13.260s	1.821ms	10	10	100.00
		hmac_long_msg	1.386m	4.557ms	10	10	100.00
		hmac_back_pressure	2.059m	3.571ms	25	25	100.00
		hmac_datapath_stress	23.038m	30.782ms	10	10	100.00
		hmac_wipe_secret	2.259m	44.537ms	10	10	100.00
		hmac_test_sha256_vectors	4.455m	8.221ms	30	30	100.00
		hmac_test_sha384_vectors	8.819m	13.598ms	75	75	100.00
		hmac_test_sha512_vectors	8.871m	27.312ms	75	75	100.00
		hmac_test_hmac256_vectors	15.980s	4.625ms	50	50	100.00
		hmac_test_hmac384_vectors	17.020s	380.211us	60	60	100.00
		hmac_test_hmac512_vectors	18.810s	416.167us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	13.260s	1.821ms	10	10	100.00
		hmac_long_msg	1.386m	4.557ms	10	10	100.00
		hmac_back_pressure	2.059m	3.571ms	25	25	100.00
		hmac_datapath_stress	23.038m	30.782ms	10	10	100.00
		hmac_burst_wr	42.930s	6.757ms	50	50	100.00
		hmac_error	1.527m	1.666ms	10	10	100.00
		hmac_wipe_secret	2.259m	44.537ms	10	10	100.00
		hmac_test_sha256_vectors	4.455m	8.221ms	30	30	100.00
		hmac_test_sha384_vectors	8.819m	13.598ms	75	75	100.00
		hmac_test_sha512_vectors	8.871m	27.312ms	75	75	100.00
		hmac_test_hmac256_vectors	15.980s	4.625ms	50	50	100.00
		hmac_test_hmac384_vectors	17.020s	380.211us	60	60	100.00
		hmac_test_hmac512_vectors	18.810s	416.167us	75	75	100.00
		hmac_stress_all	43.062m	289.437ms	50	50	100.00
V2	stress_all	hmac_stress_all	43.062m	289.437ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.930s	45.584us	50	50	100.00
V2	intr_test	hmac_intr_test	0.830s	28.928us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.450s	261.932us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.450s	261.932us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.040s	19.450us	5	5	100.00
		hmac_csr_rw	1.030s	106.280us	20	20	100.00
		hmac_csr_aliasing	6.130s	3.359ms	5	5	100.00
		hmac_same_csr_outstanding	2.060s	588.772us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.040s	19.450us	5	5	100.00
		hmac_csr_rw	1.030s	106.280us	20	20	100.00
		hmac_csr_aliasing	6.130s	3.359ms	5	5	100.00
		hmac_same_csr_outstanding	2.060s	588.772us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.320s	65.192us	5	5	100.00
		hmac_tl_intg_err	3.380s	234.161us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	3.380s	234.161us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	13.260s	1.821ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	7.010s	1.506ms	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	15.837m	347.311ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	0.860s	20.373us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.19	99.95	96.96	100.00	100.00	99.83	97.61	100.00