I2C Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.392m	8.397ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	35.520s	1.220ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.130s	20.696us	5	5	100.00
V1	csr_rw	i2c_csr_rw	1.180s	26.272us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.650s	219.263us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.240s	416.123us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.500s	35.122us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.180s	26.272us	20	20	100.00
		i2c_csr_aliasing	2.240s	416.123us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	5.640s	465.294us	4	50	8.00
V2	host_stress_all	i2c_host_stress_all	35.517m	50.067ms	10	50	20.00
V2	host_maxperf	i2c_host_perf	33.077m	73.380ms	50	50	100.00
V2	host_override	i2c_host_override	1.060s	36.985us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.100m	5.112ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.416m	4.694ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.700s	149.626us	50	50	100.00
		i2c_host_fifo_fmt_empty	25.030s	1.984ms	50	50	100.00
		i2c_host_fifo_reset_rx	12.620s	252.528us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.501m	7.550ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	38.170s	5.396ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	4.680s	525.805us	15	50	30.00
V2	target_glitch	i2c_target_glitch	4.410s	495.736us	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	21.281m	61.140ms	50	50	100.00
V2	target_maxperf	i2c_target_perf	8.070s	13.127ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.081m	4.235ms	50	50	100.00
		i2c_target_intr_smoke	9.760s	1.881ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.190s	253.119us	50	50	100.00
		i2c_target_fifo_reset_tx	2.410s	297.585us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	21.744m	62.371ms	50	50	100.00
		i2c_target_stress_rd	1.081m	4.235ms	50	50	100.00
		i2c_target_intr_stress_wr	3.687m	15.664ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	9.690s	5.753ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	1.758m	4.828ms	46	50	92.00
V2	bad_address	i2c_target_bad_addr	9.360s	12.092ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	40.870s	10.083ms	22	50	44.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	4.570s	6.255ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	2.010s	200.002us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	33.077m	73.380ms	50	50	100.00
		i2c_host_perf_precise	14.956m	24.291ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	38.170s	5.396ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	17.500s	1.023ms	48	50	96.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	4.330s	605.511us	50	50	100.00
		i2c_target_nack_acqfull_addr	3.840s	6.735ms	50	50	100.00
		i2c_target_nack_txstretch	2.340s	182.554us	33	50	66.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	25.220s	7.725ms	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.500s	1.702ms	50	50	100.00
V2	alert_test	i2c_alert_test	1.010s	27.507us	50	50	100.00
V2	intr_test	i2c_intr_test	1.070s	25.218us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.100s	125.526us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.100s	125.526us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.130s	20.696us	5	5	100.00
		i2c_csr_rw	1.180s	26.272us	20	20	100.00
		i2c_csr_aliasing	2.240s	416.123us	5	5	100.00
		i2c_same_csr_outstanding	1.630s	60.099us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.130s	20.696us	5	5	100.00
		i2c_csr_rw	1.180s	26.272us	20	20	100.00
		i2c_csr_aliasing	2.240s	416.123us	5	5	100.00
		i2c_same_csr_outstanding	1.630s	60.099us	19	20	95.00
V2		TOTAL			1617	1792	90.23
V2S	tl_intg_err	i2c_tl_intg_err	2.690s	133.705us	20	20	100.00
		i2c_sec_cm	1.400s	268.906us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.690s	133.705us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	35.720s	1.023ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.210s	1.528ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	28.870s	4.008ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1797	2042	88.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
83.90	97.25	88.95	74.17	47.62	93.83	96.41	89.11

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 83 failures:

Test i2c_host_error_intr has 46 failures.

0.i2c_host_error_intr.10605783733895212718705621555665684456302061786927415513285553118052005843518
Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 179918652 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 179918652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_error_intr.32131205787147107201634778413346734804038845157811645955530214985943049413431
Line 99, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 151427446 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 151427446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 44 more failures.

Test i2c_host_stress_all has 26 failures.

0.i2c_host_stress_all.103435998813356198389507364185269518027253917474624807090909825304669899783676
Line 120, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 1706616621 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 1706616621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all.114361707566641214567330921579635735628530648777194340245258050229877461526736
Line 156, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 67204185295 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 67204185295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 24 more failures.

Test i2c_target_stress_all_with_rand_reset has 2 failures.

1.i2c_target_stress_all_with_rand_reset.96400191571513814106664284589544561947556394316620194671961370849792184111547
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  16958120 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  16958120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.i2c_target_stress_all_with_rand_reset.31150326329597438684952612680976614845792028431039157902145005812719052672705
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  82702000 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  82702000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_host_mode_toggle has 9 failures.

6.i2c_host_mode_toggle.53277984067106431666298563592437830968330924003166013120047373361611173095202
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @   6360139 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @   6360139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.i2c_host_mode_toggle.56562868757634803624884410861698345046891177849575345051707637375047481766131
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/12.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  12587528 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  12587528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 31 failures:
- Test i2c_target_unexp_stop has 31 failures.
  - 0.i2c_target_unexp_stop.100396059080027716856215211417893831469873642659374966826260442400405772218711
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  77286959 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 126 [0x7e])
  UVM_INFO @  77286959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_unexp_stop.90297883989782809685039098946947358413134300113484347740939222384877250494147
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 118344502 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 123 [0x7b])
  UVM_INFO @ 118344502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 29 more failures.
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 28 failures:
- Test i2c_target_hrst has 28 failures.
  - 0.i2c_target_hrst.86384409789997830922853006911271065688531250341301868361864907094370274289148
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10080810415 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10080810415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_hrst.71267189832066234595834837264052158861227828450562131231114967419145829667303
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10083328182 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10083328182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 26 more failures.

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 24 failures:

Test i2c_host_mode_toggle has 13 failures.

2.i2c_host_mode_toggle.101619528332217128960719903130473242903728696128668895542031918769734560340067
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 516837154 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @23416

7.i2c_host_mode_toggle.90622788920285420457218010278494859309934313326019338915485328576826869479972
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 164919518 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @27710

... and 11 more failures.

Test i2c_host_stress_all has 11 failures.

3.i2c_host_stress_all.86077266571585765249138119168495114936333362670345250064032011286971176695400
Line 124, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 62372453320 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2518875

14.i2c_host_stress_all.66391977015076316148976476818229403248148697227821842581275710788055816212539
Line 129, in log /nightly/current_run/scratch/master/i2c-sim-vcs/14.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 59644081936 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @21340697

... and 9 more failures.

UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.40535631751475409211169907023495393429997056488968369723698100103198490432260
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 705953674 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 705953674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.111209485064106345056338570406487677153512940749424363127133134727067968171059
Line 87, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 747318715 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 747318715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 7 failures.

0.i2c_target_stress_all_with_rand_reset.35899422727724511695541007802491751361941470148595732199464620165963949849897
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1995419374 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1995419374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.i2c_target_stress_all_with_rand_reset.79764069168091503290000937526427452844179959537691926481703638431026707225395
Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4217201706 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4217201706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 17 failures:
- Test i2c_target_nack_txstretch has 17 failures.
  - 6.i2c_target_nack_txstretch.68992710784467185368373503690399649973102238692752714637438271205393590797814
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 595725808 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 595725808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.i2c_target_nack_txstretch.14630841664571284113832964560188672493299327048117365332839489941775113383763
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 307400343 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 307400343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 15 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 16 failures:
- Test i2c_target_unexp_stop has 16 failures.
  - 1.i2c_target_unexp_stop.996938164018678546690542484046775981743782243631654218698843916270588839055
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 158401708 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 158401708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.i2c_target_unexp_stop.36736892467712475506131252356077046519503855792628174546366772206705830325214
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  23242805 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  23242805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 9 failures:

Test i2c_host_mode_toggle has 9 failures.

31.i2c_host_mode_toggle.81953276715792352762680053460923793625769827862054231580897478622418406972712
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/31.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 187737265 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

33.i2c_host_mode_toggle.108317889343029505942440478222698170416431194541987231646128278983458445796
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/33.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  73145657 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 7 more failures.

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 4 failures:
- Test i2c_target_stretch has 4 failures.
  - 8.i2c_target_stretch.88766766110784889676417265845003282582723687706994855714369957785249815054086
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10012182675 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10012182675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 13.i2c_target_stretch.45037495136523211100026657362820645546284677201403953962033790033902084651585
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/13.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10004674918 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10004674918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
- Test i2c_host_mode_toggle has 3 failures.
  - 1.i2c_host_mode_toggle.32682484295140137768940611618464143276038386472503322728879222016738578683545
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  33045492 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x885bdf14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  33045492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 13.i2c_host_mode_toggle.46226792172893371205537077028597548452787045000826023003079421263885086780069
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/13.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  80640170 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x809e994, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  80640170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 3 failures:

Test i2c_target_unexp_stop has 3 failures.

18.i2c_target_unexp_stop.46194286978618271046576272361597501265139192749142663482372800185435134477882
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/18.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 1609554088 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 1609554088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.i2c_target_unexp_stop.6055084045234350089146914509185020320854372925117984444910227931881507545571
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/29.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 579989645 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 579989645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.3859233974390311908346129455279532468405035905695641389064076630920491826974
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 495735861 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 495735861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.103371195468447747690763090819746293411268322614325961702920398551627859663554
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 1884155565 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 1884155565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Error-[CNST-CIF] Constraints inconsistency failure has 2 failures:
- Test i2c_target_tx_stretch_ctrl has 2 failures.
  - 16.i2c_target_tx_stretch_ctrl.75554633037862326256336556774232657785824885317721239575093792347007047044695
    Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/16.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 46.i2c_target_tx_stretch_ctrl.97131655629158509826802951309974628900443328782963041431474950169554833243648
    Line 121, in log /nightly/current_run/scratch/master/i2c-sim-vcs/46.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 2 failures.

18.i2c_host_stress_all.46233685328944732213717468195410305123543050536408285657526709280957840368832
Line 198, in log /nightly/current_run/scratch/master/i2c-sim-vcs/18.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 12279599040 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @11967011

36.i2c_host_stress_all.91119575710375775246572672761093006424409320190715401388134544610086763415895
Line 133, in log /nightly/current_run/scratch/master/i2c-sim-vcs/36.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 11220703445 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2585135

UVM_ERROR (cip_base_vseq.sv:840) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 7.i2c_same_csr_outstanding.91760159337400798859103059702338123804878925413829858463567726863456613873029
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 110103007 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @ 110103007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 8.i2c_target_stress_all_with_rand_reset.40653017963628346178597536412102770486310919692269217485069442469333372635051
    Line 93, in log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2372662788 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2372662788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 23.i2c_host_stress_all.99701921222960375641194948871799424248421797740589330512448334265125347086409
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/23.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
Error-[NOA] Null object access has 1 failures:
- Test i2c_host_mode_toggle has 1 failures.
  - 45.i2c_host_mode_toggle.96168881645780728819420691441377566744702157704534697583282915722406968268856
    Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/45.i2c_host_mode_toggle/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```