KEYMGR Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	37.460s	9.621ms	50	50	100.00
V1	random	keymgr_random	44.750s	3.721ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.440s	23.215us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.700s	58.461us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	25.530s	2.682ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	8.410s	1.962ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.720s	65.396us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.700s	58.461us	20	20	100.00
		keymgr_csr_aliasing	8.410s	1.962ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.134m	12.680ms	49	50	98.00
V2	sideload	keymgr_sideload	36.310s	6.512ms	50	50	100.00
		keymgr_sideload_kmac	29.120s	13.459ms	50	50	100.00
		keymgr_sideload_aes	16.300s	2.094ms	50	50	100.00
		keymgr_sideload_otbn	37.370s	5.513ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	21.440s	894.477us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	6.330s	750.637us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	22.030s	5.013ms	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	59.730s	31.898ms	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	30.920s	1.953ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	19.030s	2.747ms	50	50	100.00
V2	stress_all	keymgr_stress_all	6.495m	26.281ms	49	50	98.00
V2	intr_test	keymgr_intr_test	1.240s	100.081us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.730s	174.858us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.690s	251.453us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.690s	251.453us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.440s	23.215us	5	5	100.00
		keymgr_csr_rw	1.700s	58.461us	20	20	100.00
		keymgr_csr_aliasing	8.410s	1.962ms	5	5	100.00
		keymgr_same_csr_outstanding	3.610s	757.032us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.440s	23.215us	5	5	100.00
		keymgr_csr_rw	1.700s	58.461us	20	20	100.00
		keymgr_csr_aliasing	8.410s	1.962ms	5	5	100.00
		keymgr_same_csr_outstanding	3.610s	757.032us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	14.790s	808.631us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	14.790s	808.631us	5	5	100.00
		keymgr_tl_intg_err	7.450s	851.672us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.330s	769.567us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.330s	769.567us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.330s	769.567us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.330s	769.567us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	16.180s	784.258us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	14.790s	808.631us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	14.790s	808.631us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.450s	851.672us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.330s	769.567us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.134m	12.680ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	44.750s	3.721ms	50	50	100.00
		keymgr_csr_rw	1.700s	58.461us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	44.750s	3.721ms	50	50	100.00
		keymgr_csr_rw	1.700s	58.461us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	44.750s	3.721ms	50	50	100.00
		keymgr_csr_rw	1.700s	58.461us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	6.330s	750.637us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	30.920s	1.953ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	30.920s	1.953ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	44.750s	3.721ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	16.720s	3.923ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	14.790s	808.631us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	14.790s	808.631us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	14.790s	808.631us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	14.380s	1.734ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	6.330s	750.637us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	14.790s	808.631us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	14.790s	808.631us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	14.790s	808.631us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	14.380s	1.734ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	14.380s	1.734ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	14.790s	808.631us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	14.380s	1.734ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	14.790s	808.631us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	14.380s	1.734ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	19.310s	996.736us	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			1080	1110	97.30

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.66	99.13	97.99	98.56	100.00	99.01	97.71	91.18

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
- Test keymgr_stress_all_with_rand_reset has 23 failures.
  - 2.keymgr_stress_all_with_rand_reset.46862575138875741940560818957344061075520711790977913985818981842336161934283
    Line 300, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 127079109 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 127079109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 4.keymgr_stress_all_with_rand_reset.96549368127349045463029112020015998705565366293978970420869438164552466639676
    Line 534, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1545068569 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1545068569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 21 more failures.

UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 5 failures:

Test keymgr_kmac_rsp_err has 1 failures.

7.keymgr_kmac_rsp_err.22626752110031059692467220578010137241925732789307356790475820936137020250027
Line 164, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  54839777 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  54839777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sw_invalid_input has 1 failures.

20.keymgr_sw_invalid_input.90545021098504313431342544184923377272288037759246344320900266234298843600920
Line 347, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest/run.log

  UVM_ERROR @  31981628 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  31981628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_cfg_regwen has 1 failures.

27.keymgr_cfg_regwen.34161153866305764165758830284760162341635457595016141108579440332744011016671
Line 383, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/27.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @  27678546 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  27678546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_custom_cm has 1 failures.

28.keymgr_custom_cm.18107289465421902883933775012634509727904147723614254936264184920031162711599
Line 185, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/28.keymgr_custom_cm/latest/run.log

  UVM_ERROR @  26406250 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  26406250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all_with_rand_reset has 1 failures.
- 42.keymgr_stress_all_with_rand_reset.105974729711722611930516239447435000939970995913764465029698925844088739180565
  Line 595, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 405026526 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 405026526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerIntKey for Attestation Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

16.keymgr_stress_all.21160952757751270745496325471363062078065399730635427251482874326244477677981
Line 364, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/16.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 200664198 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (3378086523591879024548010223519845165592750828936808888355307157919361030511068734883103569152931028350608982216465091729749692996501486028695483500330426 [0x407fbe33abff48a1744df5545ae837d0ab029ca87a2155e3f5ef239db552f043960901fe09901c1bfb74dc9d4bb3d4abff78f7c1dd208119d3c7efe11fa9fdba] vs 3378086523591879024548010223519845165592750828936808888355307157919361030511068734883103569152931028350608982216465091729749692996501486028695483500330426 [0x407fbe33abff48a1744df5545ae837d0ab029ca87a2155e3f5ef239db552f043960901fe09901c1bfb74dc9d4bb3d4abff78f7c1dd208119d3c7efe11fa9fdba]) AES key at state StOwnerIntKey for Attestation Aes
  UVM_INFO @ 200664198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 41.keymgr_lc_disable.114984523394828157413755105128125866228469888687710875321902411392043354357655
    Line 220, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/41.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  38276995 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_1
  UVM_INFO @  38276995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```