KMAC/MASKED Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.526m	22.135ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.470s	68.897us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.300s	22.452us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.580s	6.529ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.960s	543.332us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.050s	220.586us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.300s	22.452us	20	20	100.00
		kmac_csr_aliasing	7.960s	543.332us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.960s	26.923us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.740s	42.167us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	1.201h	2.688s	50	50	100.00
V2	burst_write	kmac_burst_write	21.391m	27.274ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.691m	242.387ms	5	5	100.00
		kmac_test_vectors_sha3_256	39.724m	306.719ms	5	5	100.00
		kmac_test_vectors_sha3_384	29.907m	276.025ms	5	5	100.00
		kmac_test_vectors_sha3_512	21.621m	364.105ms	5	5	100.00
		kmac_test_vectors_shake_128	3.708m	64.111ms	5	5	100.00
		kmac_test_vectors_shake_256	34.637m	88.604ms	5	5	100.00
		kmac_test_vectors_kmac	3.530s	117.355us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.160s	929.968us	5	5	100.00
V2	sideload	kmac_sideload	8.496m	65.155ms	50	50	100.00
V2	app	kmac_app	7.140m	127.603ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.135m	6.626ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.016m	74.618ms	50	50	100.00
V2	error	kmac_error	9.032m	124.871ms	50	50	100.00
V2	key_error	kmac_key_error	17.440s	5.030ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	9.310s	486.564us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	52.290s	1.638ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	29.370s	931.996us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.207m	5.135ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	53.750s	4.121ms	50	50	100.00
V2	stress_all	kmac_stress_all	46.951m	177.478ms	49	50	98.00
V2	intr_test	kmac_intr_test	1.240s	17.544us	50	50	100.00
V2	alert_test	kmac_alert_test	1.370s	344.924us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.690s	574.861us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.690s	574.861us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.470s	68.897us	5	5	100.00
		kmac_csr_rw	1.300s	22.452us	20	20	100.00
		kmac_csr_aliasing	7.960s	543.332us	5	5	100.00
		kmac_same_csr_outstanding	2.610s	177.302us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.470s	68.897us	5	5	100.00
		kmac_csr_rw	1.300s	22.452us	20	20	100.00
		kmac_csr_aliasing	7.960s	543.332us	5	5	100.00
		kmac_same_csr_outstanding	2.610s	177.302us	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.180s	96.260us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.180s	96.260us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.180s	96.260us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.180s	96.260us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.690s	1.824ms	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	2.031m	8.449ms	5	5	100.00
		kmac_tl_intg_err	4.630s	472.376us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.630s	472.376us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	53.750s	4.121ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.526m	22.135ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.496m	65.155ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.180s	96.260us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.031m	8.449ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.031m	8.449ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.031m	8.449ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.526m	22.135ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	53.750s	4.121ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.031m	8.449ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.144m	5.711ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.526m	22.135ms	49	50	98.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.368m	16.597ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			937	940	99.68

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.41	99.27	94.45	99.65	81.69	97.15	97.83	97.86

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:

Test kmac_smoke has 1 failures.

12.kmac_smoke.945966667118793866564735482062601666020898658676756803622291352739272591080
Line 74, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_smoke/latest/run.log

  UVM_ERROR @  34650895 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  34650895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

38.kmac_stress_all.16903433102267997441192056757136560132401845554764776094092655544993751062157
Line 154, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/38.kmac_stress_all/latest/run.log

  UVM_ERROR @ 7907082865 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 7907082865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 4.kmac_stress_all_with_rand_reset.23587323730745549748347824387128696520473400021208954387117161875192210386029
    Line 207, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1922972815 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
  UVM_INFO @ 1922972815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```