KMAC/UNMASKED Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	58.380s	13.513ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.440s	35.169us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.510s	36.543us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	16.560s	1.014ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.940s	1.913ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.450s	323.672us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.510s	36.543us	20	20	100.00
		kmac_csr_aliasing	8.940s	1.913ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.120s	16.295us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.920s	42.830us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	53.132m	225.555ms	50	50	100.00
V2	burst_write	kmac_burst_write	16.215m	141.397ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.904m	126.178ms	5	5	100.00
		kmac_test_vectors_sha3_256	24.463m	190.053ms	5	5	100.00
		kmac_test_vectors_sha3_384	23.726m	275.658ms	5	5	100.00
		kmac_test_vectors_sha3_512	15.001m	171.014ms	5	5	100.00
		kmac_test_vectors_shake_128	3.432m	25.818ms	5	5	100.00
		kmac_test_vectors_shake_256	30.101m	239.347ms	5	5	100.00
		kmac_test_vectors_kmac	2.520s	457.278us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.240s	118.095us	5	5	100.00
V2	sideload	kmac_sideload	8.072m	114.285ms	50	50	100.00
V2	app	kmac_app	5.641m	100.948ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.242m	70.228ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.499m	19.045ms	50	50	100.00
V2	error	kmac_error	6.098m	81.041ms	49	50	98.00
V2	key_error	kmac_key_error	16.150s	8.430ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.627m	10.084ms	39	50	78.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.078m	42.174ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.550s	8.105ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.060m	14.645ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	45.190s	1.043ms	50	50	100.00
V2	stress_all	kmac_stress_all	28.599m	26.859ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.180s	23.729us	50	50	100.00
V2	alert_test	kmac_alert_test	1.200s	36.591us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.850s	125.180us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.850s	125.180us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.440s	35.169us	5	5	100.00
		kmac_csr_rw	1.510s	36.543us	20	20	100.00
		kmac_csr_aliasing	8.940s	1.913ms	5	5	100.00
		kmac_same_csr_outstanding	3.020s	405.906us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.440s	35.169us	5	5	100.00
		kmac_csr_rw	1.510s	36.543us	20	20	100.00
		kmac_csr_aliasing	8.940s	1.913ms	5	5	100.00
		kmac_same_csr_outstanding	3.020s	405.906us	20	20	100.00
V2		TOTAL			728	740	98.38
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.730s	98.966us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.730s	98.966us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.730s	98.966us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.730s	98.966us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.790s	764.730us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	55.680s	5.749ms	5	5	100.00
		kmac_tl_intg_err	5.570s	600.202us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.570s	600.202us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	45.190s	1.043ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	58.380s	13.513ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.072m	114.285ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.730s	98.966us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	55.680s	5.749ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	55.680s	5.749ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	55.680s	5.749ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	58.380s	13.513ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	45.190s	1.043ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	55.680s	5.749ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.199m	16.932ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	58.380s	13.513ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.919m	4.221ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			925	940	98.40

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.57	97.69	94.41	100.00	72.73	96.04	97.74	96.40

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 2.kmac_sideload_invalid.22749401468366020392170454724843006424120043420141462322243989030223703525469
      Line 82, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/2.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10047517827 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xacb55000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10047517827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 31.kmac_sideload_invalid.26536375472825397629536023087213393980241572625236557874503447146618122631143
      Line 81, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/31.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10124969827 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xfd1000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
        UVM_INFO @ 10124969827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 5.kmac_sideload_invalid.114678319524840909616063662103188311192840277067243939405801085598190899348050
      Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/5.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10041654657 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x84456000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 10041654657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 23.kmac_sideload_invalid.84504395512540404023439792255976352868978525620747465409797909806428568918100
      Line 76, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/23.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10074335460 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x94e2c000, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
        UVM_INFO @ 10074335460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 2 failures:

  • Test kmac_sideload_invalid has 2 failures.

    • 10.kmac_sideload_invalid.74950184282537090734929394366183781449794890310690974054747861234153810459601
      Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/10.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10018022646 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x7afd4000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10018022646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 37.kmac_sideload_invalid.100734915258132290149009368708104091139145267033337909086138550023767984287500
      Line 75, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/37.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10027916201 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x170df000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
        UVM_INFO @ 10027916201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 0.kmac_sideload_invalid.97301988613738101807279561670177519658912614080702084654360626293495513895847
      Line 88, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10117988514 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe71a4000, Comparison=CompareOpEq, exp_data=0x1, call_count=14)
        UVM_INFO @ 10117988514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=38) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 8.kmac_sideload_invalid.57735085989870609568996576666515337350574884581396154094256954634627277618384
      Line 115, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/8.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10656579403 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4daca000, Comparison=CompareOpEq, exp_data=0x1, call_count=38)
        UVM_INFO @ 10656579403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 8.kmac_stress_all_with_rand_reset.94340977266450298093100495570792197584296480254728351833125890113880611454131
      Line 357, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20324649915 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 20324649915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 8.kmac_shadow_reg_errors_with_csr_rw.71032138121879236796845886735420262674519925791086310349398947198643725345141
      Line 126, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @   6686176 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (3202062745 [0xbedb9999] vs 0 [0x0]) Regname: kmac_reg_block.prefix_8.prefix_0 reset value: 0x0
        UVM_INFO @   6686176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 9.kmac_stress_all_with_rand_reset.112924713750529179217329381742743844328728929001361606880329974284136949658436
      Line 349, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5009842580 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 5009842580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 11.kmac_sideload_invalid.50631644212942775786680466864492018434282853466376836317020897949268879461075
      Line 82, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/11.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10045746978 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa4be9000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
        UVM_INFO @ 10045746978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test kmac_error has 1 failures.

    • 32.kmac_error.31204804552169095360180065247823943212226056191898428870830076866515490649444
      Line 215, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/32.kmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 35.kmac_sideload_invalid.110722409862304891040158797241913104555859033536272705298152567643086035700188
      Line 79, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/35.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10071324036 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xffcee000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
        UVM_INFO @ 10071324036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 41.kmac_sideload_invalid.109686947563756800029714314274822636065960892487282667130853262593396567883657
      Line 87, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/41.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10083680394 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x9adfa000, Comparison=CompareOpEq, exp_data=0x1, call_count=12)
        UVM_INFO @ 10083680394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---