OTBN Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 16.000s 59.349us 0 1 0.00
V1 single_binary otbn_single 28.000s 77.257us 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 14.000s 35.506us 5 5 100.00
V1 csr_rw otbn_csr_rw 8.000s 46.013us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 14.000s 1.866ms 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 8.000s 41.606us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 10.000s 38.204us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 8.000s 46.013us 20 20 100.00
otbn_csr_aliasing 8.000s 41.606us 5 5 100.00
V1 mem_walk otbn_mem_walk 37.000s 2.668ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 29.000s 1.553ms 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 40.000s 162.265us 0 10 0.00
V2 multi_error otbn_multi_err 1.100m 317.968us 0 1 0.00
V2 back_to_back otbn_multi 5.550m 1.347ms 0 10 0.00
V2 stress_all otbn_stress_all 1.983m 1.002ms 0 10 0.00
V2 lc_escalation otbn_escalate 1.783m 886.187us 18 60 30.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 6.000s 15.676us 3 5 60.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 57.000s 224.665us 0 10 0.00
V2 alert_test otbn_alert_test 9.000s 35.299us 50 50 100.00
V2 intr_test otbn_intr_test 9.000s 29.901us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 11.000s 353.613us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 11.000s 353.613us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 14.000s 35.506us 5 5 100.00
otbn_csr_rw 8.000s 46.013us 20 20 100.00
otbn_csr_aliasing 8.000s 41.606us 5 5 100.00
otbn_same_csr_outstanding 7.000s 30.470us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 14.000s 35.506us 5 5 100.00
otbn_csr_rw 8.000s 46.013us 20 20 100.00
otbn_csr_aliasing 8.000s 41.606us 5 5 100.00
otbn_same_csr_outstanding 7.000s 30.470us 20 20 100.00
V2 TOTAL 161 246 65.45
V2S mem_integrity otbn_imem_err 16.000s 71.899us 2 10 20.00
otbn_dmem_err 10.000s 48.902us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 9.000s 211.740us 0 5 0.00
otbn_controller_ispr_rdata_err 18.000s 36.030us 0 5 0.00
otbn_mac_bignum_acc_err 24.000s 145.052us 0 5 0.00
otbn_urnd_err 9.000s 24.607us 2 2 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 7.000s 21.457us 4 5 80.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 7.000s 46.869us 2 2 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 8.000s 35.897us 7 10 70.00
V2S tl_intg_err otbn_sec_cm 23.000s 99.805us 0 5 0.00
otbn_tl_intg_err 56.000s 453.398us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 29.000s 145.232us 18 20 90.00
V2S prim_fsm_check otbn_sec_cm 23.000s 99.805us 0 5 0.00
V2S prim_count_check otbn_sec_cm 23.000s 99.805us 0 5 0.00
V2S sec_cm_mem_scramble otbn_smoke 16.000s 59.349us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 10.000s 48.902us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 16.000s 71.899us 2 10 20.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 56.000s 453.398us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 1.783m 886.187us 18 60 30.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 16.000s 71.899us 2 10 20.00
otbn_dmem_err 10.000s 48.902us 0 15 0.00
otbn_zero_state_err_urnd 6.000s 15.676us 3 5 60.00
otbn_illegal_mem_acc 7.000s 21.457us 4 5 80.00
otbn_sec_cm 23.000s 99.805us 0 5 0.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 23.000s 99.805us 0 5 0.00
V2S sec_cm_scramble_key_sideload otbn_single 28.000s 77.257us 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 16.000s 71.899us 2 10 20.00
otbn_dmem_err 10.000s 48.902us 0 15 0.00
otbn_zero_state_err_urnd 6.000s 15.676us 3 5 60.00
otbn_illegal_mem_acc 7.000s 21.457us 4 5 80.00
otbn_sec_cm 23.000s 99.805us 0 5 0.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 23.000s 99.805us 0 5 0.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 1.783m 886.187us 18 60 30.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 16.000s 71.899us 2 10 20.00
otbn_dmem_err 10.000s 48.902us 0 15 0.00
otbn_zero_state_err_urnd 6.000s 15.676us 3 5 60.00
otbn_illegal_mem_acc 7.000s 21.457us 4 5 80.00
otbn_sec_cm 23.000s 99.805us 0 5 0.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 23.000s 99.805us 0 5 0.00
V2S sec_cm_data_reg_sw_sca otbn_single 28.000s 77.257us 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 18.000s 86.627us 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 15.000s 62.133us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 1.050m 1.015ms 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 1.050m 1.015ms 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 12.000s 28.876us 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 23.000s 99.805us 0 5 0.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 23.000s 99.805us 0 5 0.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 19.000s 120.684us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 23.000s 99.805us 0 5 0.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 23.000s 99.805us 0 5 0.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 17.000s 80.113us 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 17.000s 80.113us 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 13.000s 138.588us 5 7 71.43
V2S sec_cm_data_mem_sec_wipe otbn_single 28.000s 77.257us 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 28.000s 77.257us 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 28.000s 77.257us 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 5.550m 1.347ms 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 28.000s 77.257us 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 28.000s 77.257us 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 15.000s 43.475us 0 5 0.00
V2S sec_cm_key_sideload otbn_single 28.000s 77.257us 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 23.000s 99.805us 0 5 0.00
V2S TOTAL 65 163 39.88
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 13.067m 3.939ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 291 585 49.74

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
93.66 97.96 73.78 97.15 78.59 53.51 84.62 78.87 94.87

Failure Buckets