f01486e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 34.000s | 292.689us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 2.000s | 16.606us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 2.000s | 15.238us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 4.000s | 284.814us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 2.000s | 75.554us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 2.000s | 26.522us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 2.000s | 15.238us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 2.000s | 75.554us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 54.100m | 600.000ms | 33 | 50 | 66.00 |
| V2 | cnt_rollover | cnt_rollover | 1.383m | 5.484ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 32.000s | 81.372us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.520h | 2.793s | 21 | 50 | 42.00 |
| V2 | alert_test | pattgen_alert_test | 32.000s | 19.831us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 2.000s | 42.861us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 8.000s | 129.267us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 8.000s | 129.267us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 2.000s | 16.606us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 15.238us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 75.554us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 14.263us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 2.000s | 16.606us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 15.238us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 75.554us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 14.263us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 294 | 340 | 86.47 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 3.000s | 189.741us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 32.000s | 36.457us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 3.000s | 189.741us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.867m | 25.365ms | 2 | 50 | 4.00 |
| V3 | TOTAL | 2 | 50 | 4.00 | |||
| Unmapped tests | pattgen_inactive_level | 3.933m | 10.015ms | 37 | 50 | 74.00 | |
| TOTAL | 463 | 570 | 81.23 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.53 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 96.95 | 89.42 |
UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 47 failures:
0.pattgen_stress_all_with_rand_reset.97790662148022466936700361575159838119866343222737782497170361911722902618868
Line 110, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 450255136 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 450282804 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 450282804 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 450368517 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.60772965838039614523600583957620099900544744428023533887157866463875006100968
Line 122, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3924397365 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 3924428976 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3924428976 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 3924828976 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 45 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 19 failures:
0.pattgen_stress_all.62876562813685094762378478598176308602518581548572619332915646983835908040771
Line 145, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
UVM_ERROR @ 286429738 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10142
1.pattgen_stress_all.90634919924413408359675237169482479563641365715754247396949427083553014537574
Line 154, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all/latest/run.log
UVM_ERROR @ 1539327414 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10224
... and 17 more failures.
Job timed out after * minutes has 18 failures:
2.pattgen_stress_all.59294567300941022078829546218066544723321725580842215045055406855968549330821
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
7.pattgen_stress_all.48213850901605204756081644695562294085648717305854064654965012273854011562773
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 7 more failures.
9.pattgen_perf.24815003977680177453599958065272999991872635069966131814443099474530229567181
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/9.pattgen_perf/latest/run.log
Job timed out after 60 minutes
19.pattgen_perf.84232307162123088211486608760299874059832023057341793828051022296940700405117
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/19.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 7 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 9 failures:
3.pattgen_perf.75418918890361552069545634099753141052180660560961554827507641086725959554000
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.pattgen_perf.95674190796134977046474895872924370622577412168482097368850901918972496933272
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/5.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
39.pattgen_stress_all.83672518661495195226637806387706026324972157861914682704364612018247431422352
Line 110, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/39.pattgen_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 2 failures:
0.pattgen_inactive_level.61395289613394252150976964832432964392688388785320312187682683456472067259269
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10063005292 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3cf088d0, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10063005292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.pattgen_inactive_level.45547128184200914139741955571561943287479655355078369442080098354379899627570
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/11.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10004022549 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xbbb0dc10, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10004022549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 2 failures:
3.pattgen_inactive_level.66816197954292289499791861678500042138870497520515705279658486450537131240208
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10015444190 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3542dd50, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10015444190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
42.pattgen_inactive_level.32692217059582338607051996360233291236282135304081472763892237906423993747393
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/42.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10377424096 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3ea0f3d0, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10377424096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 2 failures:
7.pattgen_inactive_level.83920425204597331594621692358867664403383742342331937195022814883150328397869
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/7.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10025650378 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xeac48b90, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
UVM_INFO @ 10025650378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.pattgen_inactive_level.110209902079892011664728234242754724114009010684711514969850720410735494088466
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10968690138 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x17aaf790, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
UVM_INFO @ 10968690138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:
15.pattgen_inactive_level.16469519970466823445234007948595296350981616945632195423226602325260365647960
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10011459232 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x729d1550, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10011459232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.pattgen_inactive_level.68253957070886862300864482864069552370320071652309277002848405174019513376139
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/29.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10065824186 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe77c2f90, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10065824186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 1 failures:
29.pattgen_stress_all_with_rand_reset.30528206061304815518363925117883217270265216817176167237459691670905918608897
Line 118, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/29.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 193921251 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
31.pattgen_inactive_level.41116032772710863073788414078028521140442057239692622452210165446839802907153
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/31.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10042698995 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x19035a10, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10042698995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
33.pattgen_inactive_level.52349003621048398583920373628535432543563603235419637165791834380211974147513
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/33.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10008981855 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xd16ebd10, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
UVM_INFO @ 10008981855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
38.pattgen_inactive_level.91685893507324171367646871696422683450951118535241252112448909976663014613286
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/38.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002485023 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x89a12250, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 10002485023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
39.pattgen_inactive_level.86896124500236035387732337045071890583642069906227989704838737604990323780629
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/39.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10042660217 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x10478d10, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 10042660217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
47.pattgen_inactive_level.3021557400299562655857176905431094439219566900401410907352393779911560372776
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/47.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10009127991 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x363a13d0, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10009127991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---