ROM_CTRL/32KB Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.800s	316.862us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	7.730s	174.528us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.370s	581.413us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.190s	298.228us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.070s	169.515us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.190s	150.843us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.370s	581.413us	20	20	100.00
		rom_ctrl_csr_aliasing	6.070s	169.515us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.840s	543.472us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	8.020s	543.846us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.220s	567.024us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	27.930s	670.679us	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	11.620s	310.533us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	9.460s	547.640us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.930s	674.545us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.930s	674.545us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	7.730s	174.528us	5	5	100.00
		rom_ctrl_csr_rw	7.370s	581.413us	20	20	100.00
		rom_ctrl_csr_aliasing	6.070s	169.515us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.270s	563.958us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	7.730s	174.528us	5	5	100.00
		rom_ctrl_csr_rw	7.370s	581.413us	20	20	100.00
		rom_ctrl_csr_aliasing	6.070s	169.515us	5	5	100.00
		rom_ctrl_same_csr_outstanding	7.270s	563.958us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.806m	3.221ms	19	20	95.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	34.880s	12.994ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.637m	7.691ms	1	5	20.00
		rom_ctrl_tl_intg_err	1.022m	1.385ms	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.637m	7.691ms	1	5	20.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.637m	7.691ms	1	5	20.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.806m	3.221ms	19	20	95.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.806m	3.221ms	19	20	95.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.806m	3.221ms	19	20	95.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.806m	3.221ms	19	20	95.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.806m	3.221ms	19	20	95.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.637m	7.691ms	1	5	20.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.637m	7.691ms	1	5	20.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.800s	316.862us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.800s	316.862us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.800s	316.862us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.022m	1.385ms	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.806m	3.221ms	19	20	95.00
		rom_ctrl_kmac_err_chk	11.620s	310.533us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.806m	3.221ms	19	20	95.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.806m	3.221ms	19	20	95.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.806m	3.221ms	19	20	95.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	34.880s	12.994ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.637m	7.691ms	1	5	20.00
V2S		TOTAL			60	65	92.31
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	9.744m	22.303ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			261	266	98.12

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.24	99.59	98.66	100.00	100.00	99.64	96.80	100.00

Failure Buckets

Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 3 failures:

Test rom_ctrl_sec_cm has 3 failures.

0.rom_ctrl_sec_cm.2879775018264365240248872624443102877939162363186376462137374234338763439281
Line 220, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 44682830ps failed at 44682830ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 44682830ps failed at 44682830ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

1.rom_ctrl_sec_cm.83658982409203884520996510105154772198634871676469912461026307835324324079427
Line 283, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 27374533ps failed at 27374533ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 27374533ps failed at 27374533ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

... and 1 more failures.

UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.
  - 4.rom_ctrl_corrupt_sig_fatal_chk.45024456902399670565433789575652350038255551877272640245298446783282602429142
    Line 75, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 358093414 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 358093414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

Test rom_ctrl_sec_cm has 1 failures.

4.rom_ctrl_sec_cm.5807694634238492250783784451686873388588136583453992604438906092242291641255
Line 107, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 11996823ps failed at 11996823ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 12006823ps failed at 12006823ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'