ROM_CTRL/64KB Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	16.590s	4.203ms	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	19.790s	310.942us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	12.510s	289.801us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	12.200s	295.776us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	11.300s	298.596us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	12.950s	563.415us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	12.510s	289.801us	20	20	100.00
		rom_ctrl_csr_aliasing	11.300s	298.596us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	15.450s	2.011ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.820s	1.032ms	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	10.220s	764.715us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	57.020s	1.092ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	15.250s	2.297ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	17.340s	1.066ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	17.610s	302.556us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	17.610s	302.556us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	19.790s	310.942us	5	5	100.00
		rom_ctrl_csr_rw	12.510s	289.801us	20	20	100.00
		rom_ctrl_csr_aliasing	11.300s	298.596us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.400s	4.182ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	19.790s	310.942us	5	5	100.00
		rom_ctrl_csr_rw	12.510s	289.801us	20	20	100.00
		rom_ctrl_csr_aliasing	11.300s	298.596us	5	5	100.00
		rom_ctrl_same_csr_outstanding	14.400s	4.182ms	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	4.669m	15.479ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.111m	6.956ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	9.738m	1.303ms	4	5	80.00
		rom_ctrl_tl_intg_err	2.451m	501.722us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	9.738m	1.303ms	4	5	80.00
V2S	prim_count_check	rom_ctrl_sec_cm	9.738m	1.303ms	4	5	80.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.669m	15.479ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.669m	15.479ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.669m	15.479ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.669m	15.479ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.669m	15.479ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	9.738m	1.303ms	4	5	80.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	9.738m	1.303ms	4	5	80.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	16.590s	4.203ms	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	16.590s	4.203ms	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	16.590s	4.203ms	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.451m	501.722us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	4.669m	15.479ms	20	20	100.00
		rom_ctrl_kmac_err_chk	15.250s	2.297ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	4.669m	15.479ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	4.669m	15.479ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	4.669m	15.479ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.111m	6.956ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	9.738m	1.303ms	4	5	80.00
V2S		TOTAL			64	65	98.46
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.234m	9.039ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			265	266	99.62

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.14	99.59	98.66	100.00	100.00	99.64	96.80	99.28

Failure Buckets

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 2.rom_ctrl_sec_cm.38892403278794129615502359930842690590999114095619828777047078467261446835434
      Line 183, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 58517710ps failed at 58517710ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 58557710ps failed at 58557710ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'