RV_TIMER Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	3.050s	852.763us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.850s	46.179us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.920s	41.915us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.190s	279.446us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.070s	27.073us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.910s	69.091us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.920s	41.915us	20	20	100.00
		rv_timer_csr_aliasing	1.070s	27.073us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	5.960s	33.638ms	4	20	20.00
V2	disabled	rv_timer_disabled	4.420s	4.666ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	12.466m	1.692s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	12.466m	1.692s	10	10	100.00
V2	stress	rv_timer_stress_all	7.260s	4.523ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.920s	58.652us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.920s	15.111us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.590s	656.126us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.590s	656.126us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.850s	46.179us	5	5	100.00
		rv_timer_csr_rw	0.920s	41.915us	20	20	100.00
		rv_timer_csr_aliasing	1.070s	27.073us	5	5	100.00
		rv_timer_same_csr_outstanding	1.240s	35.604us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.850s	46.179us	5	5	100.00
		rv_timer_csr_rw	0.920s	41.915us	20	20	100.00
		rv_timer_csr_aliasing	1.070s	27.073us	5	5	100.00
		rv_timer_same_csr_outstanding	1.240s	35.604us	20	20	100.00
V2		TOTAL			194	210	92.38
V2S	tl_intg_err	rv_timer_sec_cm	1.110s	661.580us	5	5	100.00
		rv_timer_tl_intg_err	1.580s	137.642us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.580s	137.642us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	1.580s	710.781us	1	10	10.00
V3	max_value	rv_timer_max	2.060s	42.200us	1	10	10.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	54.680s	11.281ms	11	20	55.00
V3		TOTAL			13	40	32.50
		TOTAL			307	350	87.71

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.81	100.00	100.00	78.66	--	100.00	96.82	99.41

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 25 failures:
- Test rv_timer_min has 9 failures.
  - 0.rv_timer_min.67322662575592037254735008242107339329023972820200587194333847856332289708918
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 228881493 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6b551304) == 0x1
  UVM_INFO @ 228881493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_min.102940056385066514566213618227937222374868611135863966538829074743181781143763
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 710781233 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xffb63d04) == 0x1
  UVM_INFO @ 710781233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
- Test rv_timer_random_reset has 16 failures.
  - 0.rv_timer_random_reset.99967726287599186855803599525562845742150994709422709245033778414231919372697
    Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 33637786276 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x9717ef04) == 0x1
  UVM_INFO @ 33637786276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_random_reset.64922219960047925565804747938552673115584844172627087820007369611269242936787
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @  60440589 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8e547f04) == 0x1
  UVM_INFO @  60440589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 14 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 9 failures:
- Test rv_timer_max has 9 failures.
  - 0.rv_timer_max.14678756883373721933088761530884966696894816981633131933168560600379406853808
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @ 178483287 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 178483287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_max.105909556812029447327439034706333405653475023612586063232382828055093342760709
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
```
  UVM_ERROR @  42200023 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  42200023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 5 failures:
- Test rv_timer_stress_all_with_rand_reset has 5 failures.
  - 1.rv_timer_stress_all_with_rand_reset.60492504833931637570693159360107582092935043274463559045320631456909086444327
    Line 212, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 16974919102 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 16974919102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 10.rv_timer_stress_all_with_rand_reset.1913057193999808908448130930523838465722467833898650044611944074632524481580
    Line 182, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/10.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 3913033957 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 3913033957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 4 failures:

Test rv_timer_stress_all_with_rand_reset has 4 failures.

2.rv_timer_stress_all_with_rand_reset.87249644953975133290650228105306870586040564037845281813247614943345525183583
Line 248, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2183676329 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2183676329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.rv_timer_stress_all_with_rand_reset.98297942187503044162388881928842596311245635272276660651853679825000294920757
Line 171, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/7.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1880470109 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1880470109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.