SPI_DEVICE/1R1W Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.474m	555.197ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.710s	25.377us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.010s	254.521us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	35.360s	5.773ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.550s	10.111ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.070s	112.959us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.010s	254.521us	20	20	100.00
		spi_device_csr_aliasing	17.550s	10.111ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.990s	31.768us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.680s	58.497us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.190s	41.607us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.090s	1.354us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.930s	5.793us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	10.030s	253.276us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.030s	253.276us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.130s	13.592ms	50	50	100.00
		spi_device_tpm_sts_read	1.520s	470.064us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	48.840s	35.929ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	35.910s	15.571ms	50	50	100.00
		spi_device_flash_all	7.262m	339.531ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	40.240s	42.411ms	50	50	100.00
		spi_device_flash_all	7.262m	339.531ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	40.240s	42.411ms	50	50	100.00
		spi_device_flash_all	7.262m	339.531ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.262m	339.531ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	25.080s	21.517ms	50	50	100.00
		spi_device_flash_all	7.262m	339.531ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	25.080s	21.517ms	50	50	100.00
		spi_device_flash_all	7.262m	339.531ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	25.080s	21.517ms	50	50	100.00
		spi_device_flash_all	7.262m	339.531ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	25.080s	21.517ms	50	50	100.00
		spi_device_flash_all	7.262m	339.531ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	25.080s	21.517ms	50	50	100.00
		spi_device_flash_all	7.262m	339.531ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	29.210s	7.246ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.839m	55.309ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.839m	55.309ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.839m	55.309ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	37.980s	8.814ms	50	50	100.00
		spi_device_read_buffer_direct	17.950s	7.281ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.839m	55.309ms	50	50	100.00
		spi_device_flash_all	7.262m	339.531ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.262m	339.531ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.262m	339.531ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	24.750s	3.072ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	24.750s	3.072ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.474m	555.197ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.447m	176.667ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.850m	147.940ms	49	50	98.00
V2	alert_test	spi_device_alert_test	1.140s	53.858us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.130s	16.350us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.790s	507.171us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.790s	507.171us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.710s	25.377us	5	5	100.00
		spi_device_csr_rw	3.010s	254.521us	20	20	100.00
		spi_device_csr_aliasing	17.550s	10.111ms	5	5	100.00
		spi_device_same_csr_outstanding	4.760s	1.700ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.710s	25.377us	5	5	100.00
		spi_device_csr_rw	3.010s	254.521us	20	20	100.00
		spi_device_csr_aliasing	17.550s	10.111ms	5	5	100.00
		spi_device_same_csr_outstanding	4.760s	1.700ms	20	20	100.00
V2		TOTAL			939	961	97.71
V2S	tl_intg_err	spi_device_sec_cm	1.770s	505.342us	5	5	100.00
		spi_device_tl_intg_err	19.670s	1.010ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	19.670s	1.010ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.871m	63.298ms	49	50	98.00
		TOTAL			1128	1151	98.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.62	99.11	96.56	71.19	89.36	98.40	94.43	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

  • Test spi_device_mem_parity has 20 failures.

    • 0.spi_device_mem_parity.744608275745431541214514575547849936660720249266418943058526411090519778655
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @  12023239 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[95])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @  12023239 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @  12023239 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[991])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • 1.spi_device_mem_parity.62523719853305730482984811033009229237931006492514165413835304900843002038408
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   5248213 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[49])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   5248213 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   5248213 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[945])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

    • ... and 18 more failures.

• Job timed out after * minutes has 2 failures:

  • Test spi_device_stress_all has 1 failures.

    • 35.spi_device_stress_all.18834671038891796408131080889906921328253924410660974030241593358074232499458
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/35.spi_device_stress_all/latest/run.log

        Job timed out after 180 minutes
      

  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 48.spi_device_flash_mode_ignore_cmds.77347265593637382599738443907630400845811954615633745578649149564106464003797
      Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.98000148642571324014167214022622379211041731022551508112378672905424509343210
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3218441 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa8fee9 [101010001111111011101001] vs 0x0 [0])
        UVM_ERROR @   3240441 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3e44b9 [1111100100010010111001] vs 0x0 [0])
        UVM_ERROR @   3264441 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc3a1d3 [110000111010000111010011] vs 0x0 [0])
        UVM_ERROR @   3364441 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe03f23 [111000000011111100100011] vs 0x0 [0])
        UVM_ERROR @   3461441 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe3fc3b [111000111111110000111011] vs 0x0 [0])