SPI_DEVICE/2P Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	8.668m	303.771ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.370s	58.407us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.330s	320.584us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	33.110s	10.815ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	21.240s	942.451us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.060s	54.412us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.330s	320.584us	20	20	100.00
		spi_device_csr_aliasing	21.240s	942.451us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.050s	18.989us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.330s	154.769us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.180s	20.153us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.450s	16.524us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.170s	23.428us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.680s	276.336us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.680s	276.336us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.610s	5.405ms	50	50	100.00
		spi_device_tpm_sts_read	1.470s	423.026us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	54.590s	165.273ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	33.790s	8.281ms	50	50	100.00
		spi_device_flash_all	6.066m	82.852ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	36.320s	39.395ms	50	50	100.00
		spi_device_flash_all	6.066m	82.852ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	36.320s	39.395ms	50	50	100.00
		spi_device_flash_all	6.066m	82.852ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.066m	82.852ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	27.100s	2.039ms	50	50	100.00
		spi_device_flash_all	6.066m	82.852ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	27.100s	2.039ms	50	50	100.00
		spi_device_flash_all	6.066m	82.852ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	27.100s	2.039ms	50	50	100.00
		spi_device_flash_all	6.066m	82.852ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	27.100s	2.039ms	50	50	100.00
		spi_device_flash_all	6.066m	82.852ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	27.100s	2.039ms	50	50	100.00
		spi_device_flash_all	6.066m	82.852ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	35.430s	17.323ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.646m	85.189ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.646m	85.189ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.646m	85.189ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	46.380s	5.367ms	50	50	100.00
		spi_device_read_buffer_direct	14.100s	4.723ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.646m	85.189ms	50	50	100.00
		spi_device_flash_all	6.066m	82.852ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.066m	82.852ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.066m	82.852ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	24.180s	9.571ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	24.180s	9.571ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	8.668m	303.771ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	9.344m	155.723ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.294m	447.525ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.120s	17.169us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.130s	19.564us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.040s	277.938us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.040s	277.938us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.370s	58.407us	5	5	100.00
		spi_device_csr_rw	3.330s	320.584us	20	20	100.00
		spi_device_csr_aliasing	21.240s	942.451us	5	5	100.00
		spi_device_same_csr_outstanding	4.920s	799.293us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.370s	58.407us	5	5	100.00
		spi_device_csr_rw	3.330s	320.584us	20	20	100.00
		spi_device_csr_aliasing	21.240s	942.451us	5	5	100.00
		spi_device_same_csr_outstanding	4.920s	799.293us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.760s	323.545us	5	5	100.00
		spi_device_tl_intg_err	22.970s	1.070ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.970s	1.070ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	7.447m	139.322ms	50	50	100.00
		TOTAL			1151	1151	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.16	99.17	96.64	74.78	89.36	98.49	94.41	99.26