SPI_HOST Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.183m	8.658ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	17.592us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	62.649us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	231.011us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	33.407us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	25.411us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	62.649us	20	20	100.00
		spi_host_csr_aliasing	2.000s	33.407us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	17.358us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	21.519us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	3.000s	72.241us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	56.000s	4.400ms	50	50	100.00
		spi_host_error_cmd	2.000s	80.063us	50	50	100.00
		spi_host_event	8.150m	67.252ms	50	50	100.00
V2	clock_rate	spi_host_speed	1.917m	200.000ms	49	50	98.00
V2	speed	spi_host_speed	1.917m	200.000ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	1.917m	200.000ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	57.000s	2.595ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	25.580us	50	50	100.00
V2	cpol_cpha	spi_host_speed	1.917m	200.000ms	49	50	98.00
V2	full_cycle	spi_host_speed	1.917m	200.000ms	49	50	98.00
V2	duplex	spi_host_smoke	1.183m	8.658ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.183m	8.658ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.450m	13.252ms	50	50	100.00
V2	spien	spi_host_spien	4.467m	8.276ms	50	50	100.00
V2	stall	spi_host_status_stall	30.333m	230.040ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	35.000s	2.024ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	56.000s	4.400ms	50	50	100.00
V2	alert_test	spi_host_alert_test	3.000s	17.001us	50	50	100.00
V2	intr_test	spi_host_intr_test	2.000s	26.338us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	106.020us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	106.020us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	17.592us	5	5	100.00
		spi_host_csr_rw	2.000s	62.649us	20	20	100.00
		spi_host_csr_aliasing	2.000s	33.407us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	109.750us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	17.592us	5	5	100.00
		spi_host_csr_rw	2.000s	62.649us	20	20	100.00
		spi_host_csr_aliasing	2.000s	33.407us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	109.750us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	tl_intg_err	spi_host_tl_intg_err	3.000s	97.201us	20	20	100.00
		spi_host_sec_cm	3.000s	343.303us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	3.000s	97.201us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	7.483m	35.122ms	10	10	100.00
		TOTAL			838	840	99.76

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.09	96.82	93.35	98.69	94.25	73.07	100.00	95.21	90.42

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 22.spi_host_status_stall.65945097486019612419827152786265124133940045556581479209530428133919195983182
      Line 809, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/22.spi_host_status_stall/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 508766745 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
        UVM_ERROR @ 508766745 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=508767000 ps
        UVM_INFO @ 508766745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test spi_host_speed has 1 failures.

    • 27.spi_host_speed.26668265402047905609004477399577134998453444960732626401754590255654374729764
      Line 150, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/27.spi_host_speed/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---