SRAM_CTRL/MAIN Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: f01486e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.513m	3.579ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.070s	76.263us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.040s	16.589us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.960s	711.316us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.100s	15.811us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.340s	737.462us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.040s	16.589us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	15.811us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.307m	14.135ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.791m	19.044ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	19.737m	10.608ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.889m	11.523ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	36.364m	986.046ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	18.084m	21.302ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.326m	58.435ms	50	50	100.00
V2	executable	sram_ctrl_executable	23.043m	440.762ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.587m	3.004ms	50	50	100.00
		sram_ctrl_partial_access_b2b	10.501m	259.532ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.844m	3.473ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.734m	8.656ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.842m	4.227ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	23.936m	96.450ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.690s	3.353ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.325h	324.443ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.150s	121.380us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.050s	153.011us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.050s	153.011us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.070s	76.263us	5	5	100.00
		sram_ctrl_csr_rw	1.040s	16.589us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	15.811us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.150s	70.805us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.070s	76.263us	5	5	100.00
		sram_ctrl_csr_rw	1.040s	16.589us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	15.811us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.150s	70.805us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.261m	43.859ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.960s	4.634us	0	5	0.00
		sram_ctrl_tl_intg_err	3.300s	1.066ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.960s	4.634us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.300s	1.066ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	23.936m	96.450ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	23.936m	96.450ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.040s	16.589us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	23.043m	440.762ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	23.043m	440.762ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	23.043m	440.762ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.326m	58.435ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	9.240s	3.698ms	47	50	94.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.261m	43.859ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	12.550s	10.978ms	40	50	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.513m	3.579ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.513m	3.579ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	23.043m	440.762ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.960s	4.634us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.326m	58.435ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.960s	4.634us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.960s	4.634us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.513m	3.579ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.960s	4.634us	0	5	0.00
V2S		TOTAL			127	145	87.59
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.891m	13.315ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1172	1190	98.49

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.66	99.11	92.90	85.46	100.00	98.02	95.83	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 10 failures:

  • Test sram_ctrl_readback_err has 10 failures.

    • 2.sram_ctrl_readback_err.23185668939478268706965073481272908993289771539241584958814323386855967880612
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 685227643 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x21) != exp (0x2f)
        UVM_INFO @ 685227643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.sram_ctrl_readback_err.15182030886919057582976724224079665929078813196022002119942931992999070169013
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 694353139 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x57) != exp (0x5f)
        UVM_INFO @ 694353139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• Offending 'reqfifo_rvalid' has 3 failures:

  • Test sram_ctrl_mubi_enc_err has 3 failures.

    • 9.sram_ctrl_mubi_enc_err.86057482687503009430308897291071516542122915944163625356678521442397269242547
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/9.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 673082739 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 673082739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 21.sram_ctrl_mubi_enc_err.60832409423795880650178641496247760419809467435519778497114243555401022777565
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/21.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1432938832 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1432938832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(depth_o <= *'(Depth))' has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 0.sram_ctrl_sec_cm.25692319166237011364347908674709702585123874631201093776683248309625470041826
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   1527812 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   1527812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.44948686600205874421267207926625468868726396167880587256458714000664383579742
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   1493857 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   1493857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 3.sram_ctrl_sec_cm.97231177610282792691161129431621269367417441538879003925917277335919537867749
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3623170 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3623170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_sec_cm.39799440543621265406925475092206417330963503898361741367866044723306508129219
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4633529 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4633529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 1.sram_ctrl_sec_cm.39504724625683104040331579865672180467764379929351259897716901947167158206825
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   2581781 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   2581781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---