SRAM_CTRL/RET Simulation Results

Sunday October 12 2025 00:08:33 UTC

GitHub Revision: `f01486e`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.752m	658.028us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.120s	14.543us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.070s	12.283us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.940s	811.765us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.100s	19.306us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.700s	50.222us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.070s	12.283us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	19.306us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	14.110s	5.542ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.600s	658.652us	50	50	100.00
V1		TOTAL			202	205	98.54
V2	multiple_keys	sram_ctrl_multiple_keys	28.118m	25.380ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.220m	22.622ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.442m	41.569ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	18.994m	4.119ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	12.800s	1.092ms	49	50	98.00
V2	executable	sram_ctrl_executable	26.430m	78.841ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.722m	11.138ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.671m	21.269ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.603m	1.584ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.741m	296.982us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.734m	1.120ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	22.409m	91.841ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.200s	57.160us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.624h	86.330ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.070s	22.460us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.540s	1.181ms	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.540s	1.181ms	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.120s	14.543us	5	5	100.00
		sram_ctrl_csr_rw	1.070s	12.283us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	19.306us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.200s	83.875us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.120s	14.543us	5	5	100.00
		sram_ctrl_csr_rw	1.070s	12.283us	20	20	100.00
		sram_ctrl_csr_aliasing	1.100s	19.306us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.200s	83.875us	20	20	100.00
V2		TOTAL			789	790	99.87
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.920s	752.507us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.140s	18.730us	0	5	0.00
		sram_ctrl_tl_intg_err	2.970s	272.684us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.140s	18.730us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.970s	272.684us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	22.409m	91.841ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	22.409m	91.841ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.070s	12.283us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	26.430m	78.841ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	26.430m	78.841ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	26.430m	78.841ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	12.800s	1.092ms	49	50	98.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.420s	47.568us	45	50	90.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.920s	752.507us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.550s	123.294us	39	50	78.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.752m	658.028us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.752m	658.028us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	26.430m	78.841ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.140s	18.730us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	12.800s	1.092ms	49	50	98.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.140s	18.730us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.140s	18.730us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.752m	658.028us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.140s	18.730us	0	5	0.00
V2S		TOTAL			124	145	85.52
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	9.718m	9.766ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1164	1190	97.82

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.64	99.07	92.90	85.37	100.00	97.98	95.79	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 11 failures:
- Test sram_ctrl_readback_err has 11 failures.
  - 0.sram_ctrl_readback_err.4381836674743852845488194668026932813854610272199636457934906724427882726311
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 177224817 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x1c) != exp (0x6c)
  UVM_INFO @ 177224817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 11.sram_ctrl_readback_err.33454141793143440513373705673819507049093250756168728372171367645426747674179
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/11.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  34840987 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x69) != exp (0x39)
  UVM_INFO @  34840987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 5 failures:

Test sram_ctrl_sec_cm has 5 failures.

0.sram_ctrl_sec_cm.22041691251466258841844794974769072280254987648937270319240076540323120964483
Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @  19109347 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  19109347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.sram_ctrl_sec_cm.7988916415196106010089700734702623360922778718966130859711895963372878367203
Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @   3822833 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   3822833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Offending 'reqfifo_rvalid' has 5 failures:
- Test sram_ctrl_mubi_enc_err has 5 failures.
  - 10.sram_ctrl_mubi_enc_err.26737031338357872628674599976881121518524230848388149648235731897956447009104
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/10.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  28616404 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  28616404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 12.sram_ctrl_mubi_enc_err.86357920395527659630756272446544225740288217793164135082119899540772381216883
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/12.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 126387249 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 126387249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 0.sram_ctrl_csr_mem_rw_with_rand_reset.19036290208225074059468320874056903922889060971442403437514390772905132220487
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  35277283 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
  UVM_INFO @  35277283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1229) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 6.sram_ctrl_stress_all_with_rand_reset.115309211662835310586330987608638626225546369050646840507756450989695892660981
    Line 112, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/6.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 870544336 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 870544336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 9.sram_ctrl_csr_mem_rw_with_rand_reset.73469990037926973534538020664753280837498585284181091467510074517923372344530
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  46621054 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @  46621054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 15.sram_ctrl_csr_mem_rw_with_rand_reset.56476204770191024783993998690446270110097026059691833850105546354765964681541
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 114853602 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @ 114853602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test sram_ctrl_lc_escalation has 1 failures.
  - 30.sram_ctrl_lc_escalation.74373628858139890685091878026698120709323423258798162122057223912375926587258
    Line 93, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/30.sram_ctrl_lc_escalation/latest/run.log
```
  UVM_ERROR @ 262159756 ps: (mem_model.sv:48) [exp_mem_sram_ctrl_prim_reg_block] Check failed act_data === system_memory[addr] (0xf8 [11111000] vs 0xeb [11101011]) addr 0x84396a84 read out mismatch
  UVM_INFO @ 262159756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```