f01486e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 9.380s | 2.110ms | 50 | 50 | 100.00 |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 9.250s | 2.475ms | 50 | 50 | 100.00 |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 8.510s | 2.422ms | 5 | 5 | 100.00 |
| V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 9.810s | 2.509ms | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 7.780s | 4.012ms | 5 | 5 | 100.00 |
| V1 | csr_rw | sysrst_ctrl_csr_rw | 5.430s | 2.033ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 44.840s | 38.975ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 9.070s | 3.189ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 5.660s | 2.081ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 5.430s | 2.033ms | 20 | 20 | 100.00 |
| sysrst_ctrl_csr_aliasing | 9.070s | 3.189ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 165 | 165 | 100.00 | |||
| V2 | combo_detect | sysrst_ctrl_combo_detect | 7.413m | 166.783ms | 50 | 50 | 100.00 |
| V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 7.329m | 198.710ms | 94 | 100 | 94.00 |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 9.908m | 253.597ms | 49 | 50 | 98.00 |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 26.685m | 657.729ms | 45 | 50 | 90.00 |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 10.870s | 2.509ms | 50 | 50 | 100.00 |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 8.660s | 2.035ms | 50 | 50 | 100.00 |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 36.920m | 956.742ms | 50 | 50 | 100.00 |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 11.100s | 2.608ms | 50 | 50 | 100.00 |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 6.298m | 1.297s | 42 | 50 | 84.00 |
| V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 1.131m | 37.819ms | 2 | 2 | 100.00 |
| V2 | stress_all | sysrst_ctrl_stress_all | 9.342m | 181.509ms | 45 | 50 | 90.00 |
| V2 | alert_test | sysrst_ctrl_alert_test | 8.440s | 2.010ms | 50 | 50 | 100.00 |
| V2 | intr_test | sysrst_ctrl_intr_test | 6.470s | 2.013ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 7.170s | 2.043ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 7.170s | 2.043ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 7.780s | 4.012ms | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 5.430s | 2.033ms | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 9.070s | 3.189ms | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 31.760s | 8.144ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 7.780s | 4.012ms | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 5.430s | 2.033ms | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 9.070s | 3.189ms | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 31.760s | 8.144ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 667 | 692 | 96.39 | |||
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 55.710s | 22.008ms | 5 | 5 | 100.00 |
| sysrst_ctrl_tl_intg_err | 1.773m | 42.461ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 1.773m | 42.461ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 24.300s | 6.630ms | 44 | 50 | 88.00 |
| V3 | TOTAL | 44 | 50 | 88.00 | |||
| TOTAL | 901 | 932 | 96.67 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.83 | 99.50 | 97.68 | 100.00 | 96.15 | 99.59 | 98.37 | 93.49 |
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 16 failures:
Test sysrst_ctrl_stress_all has 4 failures.
2.sysrst_ctrl_stress_all.103889527260389903293733600016531642845654102904497120088355941968105480523015
Line 443, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 183334391924 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 183334475257 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 183334475257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.sysrst_ctrl_stress_all.108763853135755182002492091575997479477687792471377115607211460292646334728546
Line 382, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 6199572351 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 6199655684 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 6199655684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.
6.sysrst_ctrl_stress_all_with_rand_reset.72715222066799763440123727572903926541179373737242990116298800394739790620161
Line 414, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 264431937307 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 264432024262 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 264432024262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
27.sysrst_ctrl_stress_all_with_rand_reset.52518866924773342860169527439925941017127368292634342074896849828480703599233
Line 445, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13739613072 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 13739693071 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 13739693071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test sysrst_ctrl_ultra_low_pwr has 5 failures.
7.sysrst_ctrl_ultra_low_pwr.112301758044391956667845286313079969758758989103307249808429446389486635139109
Line 383, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 503870279797 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 503870461614 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 503870461614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.sysrst_ctrl_ultra_low_pwr.53130178292038952055044390114981003493158190306255336114336952913012579263576
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 4818241343 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 4818261960 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 4818261960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test sysrst_ctrl_edge_detect has 5 failures.
10.sysrst_ctrl_edge_detect.108151245181059807490586971165320813052280055727914048005150508888558834148031
Line 391, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_edge_detect/latest/run.log
UVM_ERROR @ 3156639997 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 3156723330 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 3156723330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.sysrst_ctrl_edge_detect.95255450750365199671109197044590095657419391532236912111491469014584003681183
Line 386, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_edge_detect/latest/run.log
UVM_ERROR @ 2625565757 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 2625645756 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2625645756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 5 failures:
Test sysrst_ctrl_stress_all has 1 failures.
13.sysrst_ctrl_stress_all.74855772623372351109805978080036949224139175940064144270808749049759420875587
Line 440, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 171818137712 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 171955637712 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 174365637712 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 174368450526 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_in_out_inverted_vseq
UVM_INFO @ 176365654332 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:80) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Starting the body from in_out_inverted_seq
Test sysrst_ctrl_ultra_low_pwr has 3 failures.
32.sysrst_ctrl_ultra_low_pwr.60910747516728063858397097875953561442109030490477296025367735681046874735576
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2179197657 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 3221697657 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3221697657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.sysrst_ctrl_ultra_low_pwr.651180123919483587957406655435585220283926797683575080473654462603398507250
Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2544088665 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 57851588665 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_ERROR @ 295874088665 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 295874088665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.
48.sysrst_ctrl_stress_all_with_rand_reset.19064696179935228380837331424209653620058623986040918723970730270659768803825
Line 435, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10633446588 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 10780946588 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 13260946588 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 13278035481 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
Issuing reset for run 8/10
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 3 failures:
8.sysrst_ctrl_combo_detect_with_pre_cond.12137570435272219537166298173739699629961603785457112187253665766301231549697
Line 405, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 38254147433 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 48457101186 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x1b
UVM_INFO @ 48457301186 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1c
UVM_INFO @ 48809541186 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1
UVM_INFO @ 48824147433 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 15
18.sysrst_ctrl_combo_detect_with_pre_cond.54986515888189223647839959323538146859072308337446930625659434351078707423546
Line 400, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 41559769838 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 51751509164 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x19
UVM_INFO @ 51751550832 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x32
UVM_INFO @ 53079769838 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 0
UVM_INFO @ 53094769838 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 19
... and 1 more failures.
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 3 failures:
24.sysrst_ctrl_combo_detect_with_pre_cond.26335361336599141162211604464562480584446005818110064722045562456015944444440
Line 406, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 33889217598 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 33889217598 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 33889217598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
51.sysrst_ctrl_combo_detect_with_pre_cond.16993617080975442528676278236517472550472538934749231788924986796230269424706
Line 410, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/51.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 38412361113 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 38412361113 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 38412361113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:36) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (* [*] vs * [*]) has 1 failures:
4.sysrst_ctrl_stress_all_with_rand_reset.28408214681256642973466205109294196480850818064379347208119997826603965469021
Line 454, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18962036968 ps: (sysrst_ctrl_pin_access_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key0_in == rdata_key0_in (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 18962036968 ps: (sysrst_ctrl_pin_access_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key2_in == rdata_key2_in (1 [0x1] vs 0 [0x0])
UVM_INFO @ 18962036968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (* [*] vs * [*]) has 1 failures:
16.sysrst_ctrl_auto_blk_key_output.90303794634623773976970497630948628248537984432899873619488024726293857400913
Line 383, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_auto_blk_key_output/latest/run.log
UVM_ERROR @ 2130539387 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 2130539387 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:122) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key2_out_value == cfg.vif.key2_out (1 [0x1] vs 0 [0x0])
UVM_INFO @ 2130539387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:109) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (* [*] vs * [*]) has 1 failures:
40.sysrst_ctrl_stress_all_with_rand_reset.44027448444842811476212784737595260805574916417882919951214904687919521671282
Line 401, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8257618367 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 8257618367 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (1 [0x1] vs 0 [0x0])
UVM_INFO @ 8257618367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:124) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (* [*] vs * [*]) Compare mismatch at PwrbIdx has 1 failures:
44.sysrst_ctrl_stress_all_with_rand_reset.107839275643085282662452385620676583988388988043299800539422295400958671399116
Line 399, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7178253209 ps: (sysrst_ctrl_edge_detect_vseq.sv:124) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at PwrbIdx
UVM_ERROR @ 7178253209 ps: (sysrst_ctrl_edge_detect_vseq.sv:124) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at EcRstIdx
UVM_INFO @ 7178253209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---