ADC_CTRL Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	20.950s	6.025ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.640s	692.585us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.000s	547.361us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.391m	29.961ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.320s	1.202ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.580s	500.482us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.000s	547.361us	20	20	100.00
		adc_ctrl_csr_aliasing	4.320s	1.202ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	21.977m	488.548ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	19.907m	490.486ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.478m	492.805ms	48	50	96.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	18.591m	485.606ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.205m	556.832ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.982m	616.365ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	22.566m	600.000ms	46	50	92.00
V2	clock_gating	adc_ctrl_clock_gating	17.821m	544.182ms	29	50	58.00
V2	poweron_counter	adc_ctrl_poweron_counter	18.520s	5.282ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.089m	44.015ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	5.895m	116.028ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	1.017h	1.681s	50	50	100.00
V2	alert_test	adc_ctrl_alert_test	2.540s	511.702us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	1.770s	491.337us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.600s	441.247us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.600s	441.247us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.640s	692.585us	5	5	100.00
		adc_ctrl_csr_rw	2.000s	547.361us	20	20	100.00
		adc_ctrl_csr_aliasing	4.320s	1.202ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	14.840s	5.266ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.640s	692.585us	5	5	100.00
		adc_ctrl_csr_rw	2.000s	547.361us	20	20	100.00
		adc_ctrl_csr_aliasing	4.320s	1.202ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	14.840s	5.266ms	20	20	100.00
V2		TOTAL			713	740	96.35
V2S	tl_intg_err	adc_ctrl_sec_cm	14.750s	7.973ms	5	5	100.00
		adc_ctrl_tl_intg_err	16.890s	8.204ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	16.890s	8.204ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	4.885m	10.000s	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			892	920	96.96

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.32	99.05	96.03	100.00	100.00	98.64	95.95	91.56

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 15 failures:
- Test adc_ctrl_clock_gating has 12 failures.
  - 1.adc_ctrl_clock_gating.17682956523091732561648890758237287341999250341348439916576381042873575605092
    Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/1.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.adc_ctrl_clock_gating.17130992413000873332452795414387610488193190615423971601107600835269899056839
    Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 10 more failures.
- Test adc_ctrl_filters_both has 2 failures.
  - 17.adc_ctrl_filters_both.35487702686870117913512232627232184236406818659257819269742465513209954700735
    Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/17.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 29.adc_ctrl_filters_both.43794199348437179291347005884992351954336255193470831305501692754672987086802
    Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/29.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 19.adc_ctrl_stress_all_with_rand_reset.95554725516392418573657061702470809629252889282877600667326954610471198813945
    Line 196, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 9 failures:
- Test adc_ctrl_clock_gating has 9 failures.
  - 0.adc_ctrl_clock_gating.88236905144136168432394074315800306981503022696351053816846812288925127924125
    Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 52754325493 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 52754325493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 13.adc_ctrl_clock_gating.46528937916450901709500448055242902799122489279639690736592248483212258507708
    Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 7174965653 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 7174965653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 4 failures:

Test adc_ctrl_filters_interrupt has 2 failures.

17.adc_ctrl_filters_interrupt.66559741230637279040673462907885128037740383676553893098006485447792535644471
Line 164, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/17.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 251147958283 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 251147958283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.adc_ctrl_filters_interrupt.30903087447166642963285459306598711970911360063045953038452001020639958541153
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/18.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 164293213569 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 164293213569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_filters_both has 2 failures.

31.adc_ctrl_filters_both.52299727916280289722965317947826396373431922630257410850804306747897067787719
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/31.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 85017031122 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 85017031122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.adc_ctrl_filters_both.20643584689741523753776857138968507459617472647548529552870228488729273515159
Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/38.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 82175982753 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 82175982753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---