AES/MASKED Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	135.648us	1	1	100.00
V1	smoke	aes_smoke	4.000s	72.289us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	68.247us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	92.512us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	969.282us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	328.699us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	119.646us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	92.512us	20	20	100.00
		aes_csr_aliasing	4.000s	328.699us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	72.289us	50	50	100.00
		aes_config_error	6.000s	216.064us	50	50	100.00
		aes_stress	9.000s	329.960us	50	50	100.00
V2	key_length	aes_smoke	4.000s	72.289us	50	50	100.00
		aes_config_error	6.000s	216.064us	50	50	100.00
		aes_stress	9.000s	329.960us	50	50	100.00
V2	back2back	aes_stress	9.000s	329.960us	50	50	100.00
		aes_b2b	33.000s	526.936us	50	50	100.00
V2	backpressure	aes_stress	9.000s	329.960us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	72.289us	50	50	100.00
		aes_config_error	6.000s	216.064us	50	50	100.00
		aes_stress	9.000s	329.960us	50	50	100.00
		aes_alert_reset	1.817m	12.579ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	81.901us	50	50	100.00
		aes_config_error	6.000s	216.064us	50	50	100.00
		aes_alert_reset	1.817m	12.579ms	50	50	100.00
V2	trigger_clear_test	aes_clear	12.000s	204.867us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	206.985us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.817m	12.579ms	50	50	100.00
V2	stress	aes_stress	9.000s	329.960us	50	50	100.00
V2	sideload	aes_stress	9.000s	329.960us	50	50	100.00
		aes_sideload	13.000s	641.000us	50	50	100.00
V2	deinitialization	aes_deinit	27.000s	1.326ms	50	50	100.00
V2	stress_all	aes_stress_all	52.000s	1.836ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	114.337us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	3.000s	255.370us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	3.000s	255.370us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	68.247us	5	5	100.00
		aes_csr_rw	3.000s	92.512us	20	20	100.00
		aes_csr_aliasing	4.000s	328.699us	5	5	100.00
		aes_same_csr_outstanding	3.000s	106.670us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	68.247us	5	5	100.00
		aes_csr_rw	3.000s	92.512us	20	20	100.00
		aes_csr_aliasing	4.000s	328.699us	5	5	100.00
		aes_same_csr_outstanding	3.000s	106.670us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	10.000s	398.552us	50	50	100.00
V2S	fault_inject	aes_fi	8.000s	720.084us	49	50	98.00
		aes_control_fi	59.000s	10.008ms	277	300	92.33
		aes_cipher_fi	58.000s	10.004ms	340	350	97.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	94.027us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	94.027us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	94.027us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	94.027us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	441.319us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	544.855us	5	5	100.00
		aes_tl_intg_err	4.000s	555.522us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	4.000s	555.522us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.817m	12.579ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	94.027us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	72.289us	50	50	100.00
		aes_stress	9.000s	329.960us	50	50	100.00
		aes_alert_reset	1.817m	12.579ms	50	50	100.00
		aes_core_fi	1.417m	10.020ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	94.027us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	301.419us	50	50	100.00
		aes_stress	9.000s	329.960us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	329.960us	50	50	100.00
		aes_sideload	13.000s	641.000us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	301.419us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	301.419us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	301.419us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	301.419us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	301.419us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	329.960us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	329.960us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	8.000s	720.084us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	8.000s	720.084us	49	50	98.00
		aes_control_fi	59.000s	10.008ms	277	300	92.33
		aes_cipher_fi	58.000s	10.004ms	340	350	97.14
		aes_ctr_fi	3.000s	52.374us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	8.000s	720.084us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	8.000s	720.084us	49	50	98.00
		aes_control_fi	59.000s	10.008ms	277	300	92.33
		aes_cipher_fi	58.000s	10.004ms	340	350	97.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	58.000s	10.004ms	340	350	97.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	8.000s	720.084us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	8.000s	720.084us	49	50	98.00
		aes_control_fi	59.000s	10.008ms	277	300	92.33
		aes_ctr_fi	3.000s	52.374us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	8.000s	720.084us	49	50	98.00
		aes_control_fi	59.000s	10.008ms	277	300	92.33
		aes_cipher_fi	58.000s	10.004ms	340	350	97.14
		aes_ctr_fi	3.000s	52.374us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.817m	12.579ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	8.000s	720.084us	49	50	98.00
		aes_control_fi	59.000s	10.008ms	277	300	92.33
		aes_cipher_fi	58.000s	10.004ms	340	350	97.14
		aes_ctr_fi	3.000s	52.374us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	8.000s	720.084us	49	50	98.00
		aes_control_fi	59.000s	10.008ms	277	300	92.33
		aes_cipher_fi	58.000s	10.004ms	340	350	97.14
		aes_ctr_fi	3.000s	52.374us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	8.000s	720.084us	49	50	98.00
		aes_control_fi	59.000s	10.008ms	277	300	92.33
		aes_ctr_fi	3.000s	52.374us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	8.000s	720.084us	49	50	98.00
		aes_control_fi	59.000s	10.008ms	277	300	92.33
		aes_cipher_fi	58.000s	10.004ms	340	350	97.14
V2S		TOTAL			946	985	96.04
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	32.000s	1.259ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1553	1602	96.94

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.28	98.56	96.34	99.38	95.32	97.99	97.78	98.36	97.99

Failure Buckets

Job timed out after * minutes has 15 failures:
- Test aes_control_fi has 14 failures.
  - 70.aes_control_fi.95525631876707354647472079243298675722224092897514401121389743403203362999175
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/70.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 80.aes_control_fi.74127182376660288983191694598275797557268044608121070842347294295726929927883
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/80.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 1 failures.
  - 78.aes_cipher_fi.78054299844840894660946101530590941457345149708048901398683935368432234985289
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/78.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 2.aes_cipher_fi.113119967497921618058199584268320634446848763065560984220816376636421855949819
    Line 147, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014789400 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014789400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 63.aes_cipher_fi.61727848758065962855915598752174227382760256029153659976431615653140314740803
    Line 139, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/63.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005996903 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005996903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 3.aes_control_fi.108336996877186028650470753537657541623014054664834263920416244730416292430100
    Line 140, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010301313 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010301313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 27.aes_control_fi.86751630860552348179917295278867193260506509956569687729568789971657460775032
    Line 144, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007969701 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007969701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.26114835231244841519751065119678719750385877231741327841739783966705030354306
Line 759, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 935496065 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 935496065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.19710425998285975659868159084685371413382757129538648846567588831466479558401
Line 220, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1151648262 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1151648262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 51.aes_core_fi.51810725219894354332452670429145055224352961070571966990955363197803786436052
    Line 138, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/51.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10031838560 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10031838560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 54.aes_core_fi.90245859207458573622356093800388852886086299974668884353486805893435436337534
    Line 145, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/54.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019553410 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019553410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 4.aes_stress_all_with_rand_reset.54110759815079305646085719414632492440578662534760961295607243729334908661058
    Line 150, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1261327151 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1261327151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.aes_stress_all_with_rand_reset.92441027280064165061162724827704438930654088368281215006238963995919588245170
    Line 162, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 482910487 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 482910487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all_with_rand_reset has 1 failures.

1.aes_stress_all_with_rand_reset.59632595316110942332922442127871298261459279222315133705248188923034597848578
Line 253, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 359104681 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 359052049 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 359104681 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 359052049 PS)
  UVM_ERROR @ 359104681 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 45.aes_fi.113433228519545044817101371564239244061680660985208290106357953739613214490451
    Line 13324, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/45.aes_fi/latest/run.log
```
  UVM_FATAL @ 720293535 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 720293535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```