AES/UNMASKED Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	66.667us	1	1	100.00
V1	smoke	aes_smoke	3.000s	74.321us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	28.000s	113.093us	5	5	100.00
V1	csr_rw	aes_csr_rw	22.000s	57.589us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	24.000s	534.510us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	18.000s	166.401us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	116.925us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	22.000s	57.589us	20	20	100.00
		aes_csr_aliasing	18.000s	166.401us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	3.000s	74.321us	50	50	100.00
		aes_config_error	3.000s	126.076us	50	50	100.00
		aes_stress	4.000s	386.386us	50	50	100.00
V2	key_length	aes_smoke	3.000s	74.321us	50	50	100.00
		aes_config_error	3.000s	126.076us	50	50	100.00
		aes_stress	4.000s	386.386us	50	50	100.00
V2	back2back	aes_stress	4.000s	386.386us	50	50	100.00
		aes_b2b	7.000s	337.929us	50	50	100.00
V2	backpressure	aes_stress	4.000s	386.386us	50	50	100.00
V2	multi_message	aes_smoke	3.000s	74.321us	50	50	100.00
		aes_config_error	3.000s	126.076us	50	50	100.00
		aes_stress	4.000s	386.386us	50	50	100.00
		aes_alert_reset	4.000s	277.030us	50	50	100.00
V2	failure_test	aes_man_cfg_err	3.000s	58.381us	50	50	100.00
		aes_config_error	3.000s	126.076us	50	50	100.00
		aes_alert_reset	4.000s	277.030us	50	50	100.00
V2	trigger_clear_test	aes_clear	5.000s	226.145us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	982.632us	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.000s	277.030us	50	50	100.00
V2	stress	aes_stress	4.000s	386.386us	50	50	100.00
V2	sideload	aes_stress	4.000s	386.386us	50	50	100.00
		aes_sideload	3.000s	114.914us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	547.403us	50	50	100.00
V2	stress_all	aes_stress_all	31.000s	4.644ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	55.876us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	28.000s	102.190us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	28.000s	102.190us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	28.000s	113.093us	5	5	100.00
		aes_csr_rw	22.000s	57.589us	20	20	100.00
		aes_csr_aliasing	18.000s	166.401us	5	5	100.00
		aes_same_csr_outstanding	16.000s	109.652us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	28.000s	113.093us	5	5	100.00
		aes_csr_rw	22.000s	57.589us	20	20	100.00
		aes_csr_aliasing	18.000s	166.401us	5	5	100.00
		aes_same_csr_outstanding	16.000s	109.652us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	4.000s	396.879us	50	50	100.00
V2S	fault_inject	aes_fi	3.000s	77.659us	48	50	96.00
		aes_control_fi	41.000s	10.006ms	278	300	92.67
		aes_cipher_fi	46.000s	200.000ms	326	350	93.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	28.000s	148.148us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	28.000s	148.148us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	28.000s	148.148us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	28.000s	148.148us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	28.000s	245.581us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	4.000s	1.310ms	5	5	100.00
		aes_tl_intg_err	30.000s	512.344us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	30.000s	512.344us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	277.030us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	28.000s	148.148us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	3.000s	74.321us	50	50	100.00
		aes_stress	4.000s	386.386us	50	50	100.00
		aes_alert_reset	4.000s	277.030us	50	50	100.00
		aes_core_fi	47.000s	10.048ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	28.000s	148.148us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	58.242us	50	50	100.00
		aes_stress	4.000s	386.386us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	386.386us	50	50	100.00
		aes_sideload	3.000s	114.914us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	58.242us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	58.242us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	58.242us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	58.242us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	58.242us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	386.386us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	386.386us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.000s	77.659us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.000s	77.659us	48	50	96.00
		aes_control_fi	41.000s	10.006ms	278	300	92.67
		aes_cipher_fi	46.000s	200.000ms	326	350	93.14
		aes_ctr_fi	3.000s	86.526us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.000s	77.659us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.000s	77.659us	48	50	96.00
		aes_control_fi	41.000s	10.006ms	278	300	92.67
		aes_cipher_fi	46.000s	200.000ms	326	350	93.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	200.000ms	326	350	93.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.000s	77.659us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.000s	77.659us	48	50	96.00
		aes_control_fi	41.000s	10.006ms	278	300	92.67
		aes_ctr_fi	3.000s	86.526us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.000s	77.659us	48	50	96.00
		aes_control_fi	41.000s	10.006ms	278	300	92.67
		aes_cipher_fi	46.000s	200.000ms	326	350	93.14
		aes_ctr_fi	3.000s	86.526us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	277.030us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.000s	77.659us	48	50	96.00
		aes_control_fi	41.000s	10.006ms	278	300	92.67
		aes_cipher_fi	46.000s	200.000ms	326	350	93.14
		aes_ctr_fi	3.000s	86.526us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.000s	77.659us	48	50	96.00
		aes_control_fi	41.000s	10.006ms	278	300	92.67
		aes_cipher_fi	46.000s	200.000ms	326	350	93.14
		aes_ctr_fi	3.000s	86.526us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.000s	77.659us	48	50	96.00
		aes_control_fi	41.000s	10.006ms	278	300	92.67
		aes_ctr_fi	3.000s	86.526us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.000s	77.659us	48	50	96.00
		aes_control_fi	41.000s	10.006ms	278	300	92.67
		aes_cipher_fi	46.000s	200.000ms	326	350	93.14
V2S		TOTAL			933	985	94.72
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	16.000s	441.796us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1540	1602	96.13

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.21	97.64	94.67	98.80	93.00	98.07	92.59	98.08	98.59

Failure Buckets

Job timed out after * minutes has 28 failures:
- Test aes_control_fi has 16 failures.
  - 4.aes_control_fi.47159040115615568420988695660257254608741755142799368234075582173727940737079
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 8.aes_control_fi.40206237251304594032924360450196771643176442107924349348470454715743660497264
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 14 more failures.
- Test aes_cipher_fi has 12 failures.
  - 18.aes_cipher_fi.77881056489215904603684790466575572959655906505265336217753518943453884085609
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 24.aes_cipher_fi.63192814766062478628449849542294033713884642721587457788656195287927013888765
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/24.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 2.aes_cipher_fi.39640637350874705137052310856960511831634584698988460483986335813926569296101
    Line 143, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006541056 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006541056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.aes_cipher_fi.75646819454001075027528116550205795425163430108772269807211671142568931411541
    Line 145, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004837155 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004837155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.44486359754953382285009075325743613516959250545872411677266934384961278030040
Line 439, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 596820337 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 596820337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.1732865241813632927604113414917334952548333186643264444334771865450877168012
Line 1165, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 407450899 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 407450899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 20.aes_control_fi.103326186419896007752415324404197286624795162289172056719512528002686633054265
    Line 143, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006092403 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006092403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 89.aes_control_fi.39978919128791594802537814523654697060418407469491443406255554486652759972494
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/89.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10024853683 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10024853683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 2 failures:

Test aes_fi has 2 failures.

19.aes_fi.65345043687973473569051433829404575599828355701831004665881734225877784311713
Line 3524, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/19.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 89567031 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 89476122 PS)
  UVM_ERROR @  89567031 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  89567031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.aes_fi.60889845135203043560284543884939498372504717268032346139413072890871138222399
Line 2645, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/44.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 15532026 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 15511618 PS)
  UVM_ERROR @  15532026 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  15532026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 33.aes_core_fi.103709756625151269705896407777774376689516175902371643066392793729231604627811
    Line 140, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003975948 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003975948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 42.aes_core_fi.62415831900853133404806126162597202346549467538942074608273776533250781657362
    Line 149, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/42.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004251918 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004251918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.15935894309436296792095283369772272611819915467922723735901711451993783043502
    Line 253, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 993322745 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 993322745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.51131172648591496451877585591120755914153073604329433637029526481617279785777
    Line 142, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @   8028410 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @   8028410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.93816143892755887329690317136812811641713228268183665719660487433909883361788
    Line 821, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 580179536 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 580179536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.34320285523959412957196728403386774885248409672386493895643732760545376149808
    Line 163, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 223399664 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 223399664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 37.aes_core_fi.13337393242455103100239472833981348830413124896866521162153449001176073163479
    Line 135, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/37.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10047819980 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0xa78aa84, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10047819980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 38.aes_core_fi.43896202404451632658734094151990938680392758966510845439291394720377518364062
    Line 135, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10040816864 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10040816864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 200.aes_cipher_fi.3635876146772349657324779242260425903160073717883338518651307971615809208070
    Line 135, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/200.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```