CSRNG Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	326.563us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	112.412us	5	5	100.00
V1	csr_rw	csrng_csr_rw	4.000s	69.005us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	50.000s	5.784ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	332.660us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	4.000s	173.229us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	4.000s	69.005us	20	20	100.00
		csrng_csr_aliasing	7.000s	332.660us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	18.000s	1.080ms	196	200	98.00
V2	alerts	csrng_alert	45.000s	3.639ms	500	500	100.00
V2	err	csrng_err	4.000s	140.552us	494	500	98.80
V2	cmds	csrng_cmds	6.450m	34.134ms	50	50	100.00
V2	life cycle	csrng_cmds	6.450m	34.134ms	50	50	100.00
V2	stress_all	csrng_stress_all	18.167m	64.022ms	47	50	94.00
V2	intr_test	csrng_intr_test	3.000s	29.650us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	243.806us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	9.000s	429.243us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	9.000s	429.243us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	112.412us	5	5	100.00
		csrng_csr_rw	4.000s	69.005us	20	20	100.00
		csrng_csr_aliasing	7.000s	332.660us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	210.968us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	112.412us	5	5	100.00
		csrng_csr_rw	4.000s	69.005us	20	20	100.00
		csrng_csr_aliasing	7.000s	332.660us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	210.968us	20	20	100.00
V2		TOTAL			1427	1440	99.10
V2S	tl_intg_err	csrng_sec_cm	7.000s	554.206us	5	5	100.00
		csrng_tl_intg_err	9.000s	430.991us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	169.935us	50	50	100.00
		csrng_csr_rw	4.000s	69.005us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	45.000s	3.639ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	18.167m	64.022ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	18.000s	1.080ms	196	200	98.00
		csrng_err	4.000s	140.552us	494	500	98.80
		csrng_sec_cm	7.000s	554.206us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	18.000s	1.080ms	196	200	98.00
		csrng_err	4.000s	140.552us	494	500	98.80
		csrng_sec_cm	7.000s	554.206us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	18.000s	1.080ms	196	200	98.00
		csrng_err	4.000s	140.552us	494	500	98.80
		csrng_sec_cm	7.000s	554.206us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	18.000s	1.080ms	196	200	98.00
		csrng_err	4.000s	140.552us	494	500	98.80
		csrng_sec_cm	7.000s	554.206us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	18.000s	1.080ms	196	200	98.00
		csrng_err	4.000s	140.552us	494	500	98.80
		csrng_sec_cm	7.000s	554.206us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	18.000s	1.080ms	196	200	98.00
		csrng_err	4.000s	140.552us	494	500	98.80
		csrng_sec_cm	7.000s	554.206us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	18.000s	1.080ms	196	200	98.00
		csrng_err	4.000s	140.552us	494	500	98.80
		csrng_sec_cm	7.000s	554.206us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	45.000s	3.639ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	18.000s	1.080ms	196	200	98.00
		csrng_err	4.000s	140.552us	494	500	98.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	18.167m	64.022ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	45.000s	3.639ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	9.000s	430.991us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	18.000s	1.080ms	196	200	98.00
		csrng_err	4.000s	140.552us	494	500	98.80
		csrng_sec_cm	7.000s	554.206us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	18.000s	1.080ms	196	200	98.00
		csrng_err	4.000s	140.552us	494	500	98.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	18.000s	1.080ms	196	200	98.00
		csrng_err	4.000s	140.552us	494	500	98.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	18.000s	1.080ms	196	200	98.00
		csrng_err	4.000s	140.552us	494	500	98.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	18.000s	1.080ms	196	200	98.00
		csrng_err	4.000s	140.552us	494	500	98.80
		csrng_sec_cm	7.000s	554.206us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	18.000s	1.080ms	196	200	98.00
		csrng_err	4.000s	140.552us	494	500	98.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	11.583m	65.570ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1617	1630	99.20

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.64	98.55	96.43	99.97	97.08	92.08	100.00	95.61	90.57

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed has 9 failures:
  • Test csrng_err has 5 failures.

    • 9.csrng_err.8985874313327925325152494135941747320082805964993291269049854232367412855493
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/9.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 12613603 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @  12613603 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  12613603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 37.csrng_err.36627548587568921002918593974150910256966849367127006201737646668256029275092
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/37.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 15214179 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @  15214179 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  15214179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

  • Test csrng_intr has 4 failures.

    • 19.csrng_intr.13698498676103444629921736772667106487757709026129450927458774291751457129528
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/19.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 66003800 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @  66003800 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  66003800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 44.csrng_intr.100540713942073076667283385925790233933658266907543031713158006918302447679858
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/44.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 212858197 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @ 212858197 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @ 212858197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
  • Test csrng_stress_all has 3 failures.

    • 16.csrng_stress_all.23236646233240872756388897879120696388524413081288930020354692094420581842500
      Line 148, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/16.csrng_stress_all/latest/run.log

        UVM_ERROR @ 271570491 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 271570491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 37.csrng_stress_all.69563812688411054696345006594348045216447588133977517011777954332764674540670
      Line 171, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/37.csrng_stress_all/latest/run.log

        UVM_ERROR @  84200835 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @  84200835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
  • Test csrng_err has 1 failures.

    • 409.csrng_err.81888661168456537055175174646229213453518288995900549878068134147293910999273
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/409.csrng_err/latest/run.log

        UVM_ERROR @  10199283 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
        UVM_INFO @  10199283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---