EDN Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.410s	20.506us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.280s	17.484us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.230s	16.393us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.010s	262.934us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.760s	72.508us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.690s	55.854us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.230s	16.393us	20	20	100.00
		edn_csr_aliasing	1.760s	72.508us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	4.120s	298.864us	300	300	100.00
V2	csrng_commands	edn_genbits	4.120s	298.864us	300	300	100.00
V2	genbits	edn_genbits	4.120s	298.864us	300	300	100.00
V2	interrupts	edn_intr	1.610s	22.768us	50	50	100.00
V2	alerts	edn_alert	1.810s	172.403us	200	200	100.00
V2	errs	edn_err	1.740s	90.318us	100	100	100.00
V2	disable	edn_disable	1.340s	13.448us	50	50	100.00
		edn_disable_auto_req_mode	1.950s	53.402us	50	50	100.00
V2	stress_all	edn_stress_all	7.840s	491.010us	50	50	100.00
V2	intr_test	edn_intr_test	1.320s	16.404us	50	50	100.00
V2	alert_test	edn_alert_test	5.570s	331.520us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.110s	421.237us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.110s	421.237us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.280s	17.484us	5	5	100.00
		edn_csr_rw	1.230s	16.393us	20	20	100.00
		edn_csr_aliasing	1.760s	72.508us	5	5	100.00
		edn_same_csr_outstanding	1.750s	30.039us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.280s	17.484us	5	5	100.00
		edn_csr_rw	1.230s	16.393us	20	20	100.00
		edn_csr_aliasing	1.760s	72.508us	5	5	100.00
		edn_same_csr_outstanding	1.750s	30.039us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	8.340s	1.418ms	5	5	100.00
		edn_tl_intg_err	2.970s	104.835us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.310s	30.058us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.810s	172.403us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	8.340s	1.418ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	8.340s	1.418ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	8.340s	1.418ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	8.340s	1.418ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.810s	172.403us	200	200	100.00
		edn_sec_cm	8.340s	1.418ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.810s	172.403us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.970s	104.835us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.070m	110.973ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1102	1130	97.52

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.64	98.87	94.11	97.02	92.44	96.33	97.56	93.13

Failure Buckets

• Job timed out after * minutes has 27 failures:
  • Test edn_stress_all_with_rand_reset has 27 failures.

    • 1.edn_stress_all_with_rand_reset.15545487152203699056086010340100867400235004423230211580465208078420377014448
      Log /nightly/current_run/scratch/master/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 2.edn_stress_all_with_rand_reset.86536564363172515597572624557883948480158374194702663393889139560318851681509
      Log /nightly/current_run/scratch/master/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 25 more failures.

• UVM_ERROR (cip_base_vseq.sv:1142) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 45.edn_stress_all_with_rand_reset.93925042472674154775939289693112821886285556517597788091739245999059721028432
      Line 132, in log /nightly/current_run/scratch/master/edn-sim-vcs/45.edn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2027870830 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 2027870830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---