HMAC Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	15.660s	3.863ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.260s	40.446us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.350s	37.125us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	7.520s	422.187us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.650s	2.339ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	16.901m	115.133ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.350s	37.125us	20	20	100.00
		hmac_csr_aliasing	6.650s	2.339ms	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.223m	10.126ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.564m	3.407ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.583m	67.177ms	30	30	100.00
		hmac_test_sha384_vectors	8.685m	24.401ms	75	75	100.00
		hmac_test_sha512_vectors	9.330m	54.925ms	75	75	100.00
		hmac_test_hmac256_vectors	15.320s	509.205us	50	50	100.00
		hmac_test_hmac384_vectors	18.250s	1.548ms	60	60	100.00
		hmac_test_hmac512_vectors	20.680s	420.024us	75	75	100.00
V2	burst_wr	hmac_burst_wr	55.170s	17.764ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	12.929m	4.413ms	10	10	100.00
V2	error	hmac_error	1.599m	23.410ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.430m	4.590ms	10	10	100.00
V2	save_and_restore	hmac_smoke	15.660s	3.863ms	10	10	100.00
		hmac_long_msg	1.223m	10.126ms	10	10	100.00
		hmac_back_pressure	1.564m	3.407ms	25	25	100.00
		hmac_datapath_stress	12.929m	4.413ms	10	10	100.00
		hmac_burst_wr	55.170s	17.764ms	50	50	100.00
		hmac_stress_all	55.193m	135.119ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	15.660s	3.863ms	10	10	100.00
		hmac_long_msg	1.223m	10.126ms	10	10	100.00
		hmac_back_pressure	1.564m	3.407ms	25	25	100.00
		hmac_datapath_stress	12.929m	4.413ms	10	10	100.00
		hmac_wipe_secret	1.430m	4.590ms	10	10	100.00
		hmac_test_sha256_vectors	4.583m	67.177ms	30	30	100.00
		hmac_test_sha384_vectors	8.685m	24.401ms	75	75	100.00
		hmac_test_sha512_vectors	9.330m	54.925ms	75	75	100.00
		hmac_test_hmac256_vectors	15.320s	509.205us	50	50	100.00
		hmac_test_hmac384_vectors	18.250s	1.548ms	60	60	100.00
		hmac_test_hmac512_vectors	20.680s	420.024us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	15.660s	3.863ms	10	10	100.00
		hmac_long_msg	1.223m	10.126ms	10	10	100.00
		hmac_back_pressure	1.564m	3.407ms	25	25	100.00
		hmac_datapath_stress	12.929m	4.413ms	10	10	100.00
		hmac_burst_wr	55.170s	17.764ms	50	50	100.00
		hmac_error	1.599m	23.410ms	10	10	100.00
		hmac_wipe_secret	1.430m	4.590ms	10	10	100.00
		hmac_test_sha256_vectors	4.583m	67.177ms	30	30	100.00
		hmac_test_sha384_vectors	8.685m	24.401ms	75	75	100.00
		hmac_test_sha512_vectors	9.330m	54.925ms	75	75	100.00
		hmac_test_hmac256_vectors	15.320s	509.205us	50	50	100.00
		hmac_test_hmac384_vectors	18.250s	1.548ms	60	60	100.00
		hmac_test_hmac512_vectors	20.680s	420.024us	75	75	100.00
		hmac_stress_all	55.193m	135.119ms	50	50	100.00
V2	stress_all	hmac_stress_all	55.193m	135.119ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.960s	16.545us	50	50	100.00
V2	intr_test	hmac_intr_test	1.050s	17.256us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.520s	555.662us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.520s	555.662us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.260s	40.446us	5	5	100.00
		hmac_csr_rw	1.350s	37.125us	20	20	100.00
		hmac_csr_aliasing	6.650s	2.339ms	5	5	100.00
		hmac_same_csr_outstanding	2.360s	527.737us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.260s	40.446us	5	5	100.00
		hmac_csr_rw	1.350s	37.125us	20	20	100.00
		hmac_csr_aliasing	6.650s	2.339ms	5	5	100.00
		hmac_same_csr_outstanding	2.360s	527.737us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.400s	287.510us	5	5	100.00
		hmac_tl_intg_err	3.550s	225.271us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	3.550s	225.271us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	15.660s	3.863ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	9.170s	165.023us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	7.370m	24.313ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	1.330s	28.381us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.75	99.95	96.80	100.00	97.06	99.83	97.61	100.00