I2C Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 host_smoke i2c_host_smoke 1.274m 4.105ms 50 50 100.00
V1 target_smoke i2c_target_smoke 48.280s 3.611ms 50 50 100.00
V1 csr_hw_reset i2c_csr_hw_reset 1.090s 19.415us 5 5 100.00
V1 csr_rw i2c_csr_rw 1.060s 69.545us 20 20 100.00
V1 csr_bit_bash i2c_csr_bit_bash 3.360s 442.058us 5 5 100.00
V1 csr_aliasing i2c_csr_aliasing 1.980s 464.797us 5 5 100.00
V1 csr_mem_rw_with_rand_reset i2c_csr_mem_rw_with_rand_reset 1.550s 40.206us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr i2c_csr_rw 1.060s 69.545us 20 20 100.00
i2c_csr_aliasing 1.980s 464.797us 5 5 100.00
V1 TOTAL 155 155 100.00
V2 host_error_intr i2c_host_error_intr 14.410s 391.578us 3 50 6.00
V2 host_stress_all i2c_host_stress_all 37.687m 176.832ms 11 50 22.00
V2 host_maxperf i2c_host_perf 42.356m 27.554ms 50 50 100.00
V2 host_override i2c_host_override 1.070s 28.512us 50 50 100.00
V2 host_fifo_watermark i2c_host_fifo_watermark 4.698m 10.468ms 50 50 100.00
V2 host_fifo_overflow i2c_host_fifo_overflow 2.108m 9.499ms 50 50 100.00
V2 host_fifo_reset i2c_host_fifo_reset_fmt 1.660s 402.723us 50 50 100.00
i2c_host_fifo_fmt_empty 20.780s 1.821ms 50 50 100.00
i2c_host_fifo_reset_rx 11.080s 800.993us 50 50 100.00
V2 host_fifo_full i2c_host_fifo_full 3.350m 3.792ms 50 50 100.00
V2 host_timeout i2c_host_stretch_timeout 41.990s 20.861ms 50 50 100.00
V2 i2c_host_mode_toggle i2c_host_mode_toggle 7.460s 448.938us 9 50 18.00
V2 target_glitch i2c_target_glitch 3.760s 455.425us 0 2 0.00
V2 target_stress_all i2c_target_stress_all 20.339m 60.138ms 50 50 100.00
V2 target_maxperf i2c_target_perf 8.660s 1.093ms 50 50 100.00
V2 target_fifo_empty i2c_target_stress_rd 1.044m 1.750ms 50 50 100.00
i2c_target_intr_smoke 9.860s 2.107ms 50 50 100.00
V2 target_fifo_reset i2c_target_fifo_reset_acq 2.420s 274.536us 50 50 100.00
i2c_target_fifo_reset_tx 2.280s 270.545us 50 50 100.00
V2 target_fifo_full i2c_target_stress_wr 16.347m 59.830ms 50 50 100.00
i2c_target_stress_rd 1.044m 1.750ms 50 50 100.00
i2c_target_intr_stress_wr 7.533m 25.813ms 49 50 98.00
V2 target_timeout i2c_target_timeout 10.250s 3.194ms 50 50 100.00
V2 target_clock_stretch i2c_target_stretch 3.346m 4.626ms 48 50 96.00
V2 bad_address i2c_target_bad_addr 8.540s 5.662ms 50 50 100.00
V2 target_mode_glitch i2c_target_hrst 37.770s 10.150ms 26 50 52.00
V2 target_fifo_watermark i2c_target_fifo_watermarks_acq 3.930s 2.995ms 50 50 100.00
i2c_target_fifo_watermarks_tx 2.350s 709.271us 50 50 100.00
V2 host_mode_config_perf i2c_host_perf 42.356m 27.554ms 50 50 100.00
i2c_host_perf_precise 5.553m 24.731ms 50 50 100.00
V2 host_mode_clock_stretching i2c_host_stretch_timeout 41.990s 20.861ms 50 50 100.00
V2 target_mode_tx_stretch_ctrl i2c_target_tx_stretch_ctrl 10.500s 1.210ms 47 50 94.00
V2 target_mode_nack_generation i2c_target_nack_acqfull 4.220s 630.558us 50 50 100.00
i2c_target_nack_acqfull_addr 4.080s 2.227ms 50 50 100.00
i2c_target_nack_txstretch 2.210s 809.776us 39 50 78.00
V2 host_mode_halt_on_nak i2c_host_may_nack 27.860s 1.713ms 50 50 100.00
V2 target_mode_smbus_maxlen i2c_target_smbus_maxlen 3.530s 2.288ms 50 50 100.00
V2 alert_test i2c_alert_test 1.010s 38.716us 50 50 100.00
V2 intr_test i2c_intr_test 0.960s 21.147us 50 50 100.00
V2 tl_d_oob_addr_access i2c_tl_errors 2.290s 166.248us 20 20 100.00
V2 tl_d_illegal_access i2c_tl_errors 2.290s 166.248us 20 20 100.00
V2 tl_d_outstanding_access i2c_csr_hw_reset 1.090s 19.415us 5 5 100.00
i2c_csr_rw 1.060s 69.545us 20 20 100.00
i2c_csr_aliasing 1.980s 464.797us 5 5 100.00
i2c_same_csr_outstanding 1.450s 512.388us 20 20 100.00
V2 tl_d_partial_access i2c_csr_hw_reset 1.090s 19.415us 5 5 100.00
i2c_csr_rw 1.060s 69.545us 20 20 100.00
i2c_csr_aliasing 1.980s 464.797us 5 5 100.00
i2c_same_csr_outstanding 1.450s 512.388us 20 20 100.00
V2 TOTAL 1622 1792 90.51
V2S tl_intg_err i2c_tl_intg_err 2.210s 153.212us 20 20 100.00
i2c_sec_cm 1.470s 129.618us 5 5 100.00
V2S sec_cm_bus_integrity i2c_tl_intg_err 2.210s 153.212us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 host_stress_all_with_rand_reset i2c_host_stress_all_with_rand_reset 31.520s 1.042ms 0 10 0.00
V3 target_error_intr i2c_target_unexp_stop 3.480s 2.068ms 0 50 0.00
V3 target_stress_all_with_rand_reset i2c_target_stress_all_with_rand_reset 37.550s 1.552ms 0 10 0.00
V3 TOTAL 0 70 0.00
TOTAL 1802 2042 88.25

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
84.25 97.37 89.44 74.17 48.81 94.11 96.41 89.43

Failure Buckets