KEYMGR Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	28.750s	5.204ms	49	50	98.00
V1	random	keymgr_random	37.810s	11.627ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.150s	30.441us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.180s	76.101us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	23.200s	2.667ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	9.270s	1.333ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.800s	71.378us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.180s	76.101us	20	20	100.00
		keymgr_csr_aliasing	9.270s	1.333ms	5	5	100.00
V1		TOTAL			154	155	99.35
V2	cfgen_during_op	keymgr_cfg_regwen	1.172m	2.000ms	50	50	100.00
V2	sideload	keymgr_sideload	26.070s	6.580ms	50	50	100.00
		keymgr_sideload_kmac	24.760s	1.552ms	50	50	100.00
		keymgr_sideload_aes	23.740s	1.283ms	50	50	100.00
		keymgr_sideload_otbn	24.750s	1.367ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	16.130s	2.728ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	32.460s	905.174us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	8.740s	385.715us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	59.260s	19.210ms	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	28.310s	3.933ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	9.120s	473.193us	49	50	98.00
V2	stress_all	keymgr_stress_all	12.048m	115.591ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.880s	22.707us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.490s	148.484us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.210s	363.860us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.210s	363.860us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.150s	30.441us	5	5	100.00
		keymgr_csr_rw	1.180s	76.101us	20	20	100.00
		keymgr_csr_aliasing	9.270s	1.333ms	5	5	100.00
		keymgr_same_csr_outstanding	2.720s	446.365us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.150s	30.441us	5	5	100.00
		keymgr_csr_rw	1.180s	76.101us	20	20	100.00
		keymgr_csr_aliasing	9.270s	1.333ms	5	5	100.00
		keymgr_same_csr_outstanding	2.720s	446.365us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	16.200s	821.167us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	16.200s	821.167us	5	5	100.00
		keymgr_tl_intg_err	7.050s	1.001ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.380s	846.260us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.380s	846.260us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.380s	846.260us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.380s	846.260us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	14.590s	2.627ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	16.200s	821.167us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	16.200s	821.167us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.050s	1.001ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.380s	846.260us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.172m	2.000ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	37.810s	11.627ms	50	50	100.00
		keymgr_csr_rw	1.180s	76.101us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	37.810s	11.627ms	50	50	100.00
		keymgr_csr_rw	1.180s	76.101us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	37.810s	11.627ms	50	50	100.00
		keymgr_csr_rw	1.180s	76.101us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	32.460s	905.174us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	28.310s	3.933ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	28.310s	3.933ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	37.810s	11.627ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	37.450s	4.709ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	16.200s	821.167us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	16.200s	821.167us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	16.200s	821.167us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	21.800s	2.677ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	32.460s	905.174us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	16.200s	821.167us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	16.200s	821.167us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	16.200s	821.167us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	21.800s	2.677ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	21.800s	2.677ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	16.200s	821.167us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	21.800s	2.677ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	16.200s	821.167us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	21.800s	2.677ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	23.250s	2.676ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1085	1110	97.75

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.65	99.13	98.18	98.37	100.00	99.01	97.71	91.13

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 18 failures:
- Test keymgr_stress_all_with_rand_reset has 18 failures.
  - 0.keymgr_stress_all_with_rand_reset.108816151392810261118349860209980871373625431398045241984822138633924321334501
    Line 261, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 131201246 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 131201246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.keymgr_stress_all_with_rand_reset.30641344151878707441544104715622471899039942177669721081935918978353358766186
    Line 420, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 634561387 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 634561387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.

UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 7 failures:

Test keymgr_sync_async_fault_cross has 1 failures.

14.keymgr_sync_async_fault_cross.99402050637615279044487311776615472062934867061600820242896243274124731874843
Line 86, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest/run.log

  UVM_ERROR @   7275139 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   7275139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all_with_rand_reset has 1 failures.
- 28.keymgr_stress_all_with_rand_reset.51440016389918432776891534443254569407620991878578664913698182481429641104280
  Line 886, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 175286987 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 175286987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test keymgr_stress_all has 2 failures.

38.keymgr_stress_all.83489381611594728946514959961219645182041488490639141856919883129482211488186
Line 372, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/38.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 226734734 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 226734734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.keymgr_stress_all.108980652172846853499389237748775942708771011338001256047556150786810447611871
Line 875, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/47.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 576361301 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 576361301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_smoke has 1 failures.

39.keymgr_smoke.104352892564692964020731178847926988778480854528190117037903707792802316604951
Line 106, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/39.keymgr_smoke/latest/run.log

  UVM_ERROR @  13461532 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  13461532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sw_invalid_input has 1 failures.

39.keymgr_sw_invalid_input.42173988876728251362138549628108941265111822959968495726573174140538826570468
Line 426, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/39.keymgr_sw_invalid_input/latest/run.log

  UVM_ERROR @  36890262 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  36890262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more tests.