KMAC/MASKED Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.457m	4.134ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.390s	21.691us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.530s	145.622us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	18.430s	8.924ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.660s	1.999ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.960s	76.977us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.530s	145.622us	20	20	100.00
		kmac_csr_aliasing	7.660s	1.999ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.190s	13.879us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.820s	41.505us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	1.169h	630.614ms	50	50	100.00
V2	burst_write	kmac_burst_write	23.855m	67.503ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.045m	83.372ms	5	5	100.00
		kmac_test_vectors_sha3_256	33.742m	119.449ms	5	5	100.00
		kmac_test_vectors_sha3_384	28.211m	272.636ms	5	5	100.00
		kmac_test_vectors_sha3_512	22.494m	46.653ms	5	5	100.00
		kmac_test_vectors_shake_128	44.213m	779.538ms	5	5	100.00
		kmac_test_vectors_shake_256	40.456m	348.988ms	5	5	100.00
		kmac_test_vectors_kmac	3.800s	926.035us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.330s	231.587us	5	5	100.00
V2	sideload	kmac_sideload	8.813m	19.879ms	50	50	100.00
V2	app	kmac_app	7.080m	19.180ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	7.458m	77.836ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.394m	17.974ms	50	50	100.00
V2	error	kmac_error	8.933m	85.159ms	50	50	100.00
V2	key_error	kmac_key_error	17.280s	1.748ms	49	50	98.00
V2	sideload_invalid	kmac_sideload_invalid	10.580s	556.926us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.610s	5.133ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	42.960s	1.769ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.347m	31.988ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	40.580s	678.816us	50	50	100.00
V2	stress_all	kmac_stress_all	46.472m	161.123ms	50	50	100.00
V2	intr_test	kmac_intr_test	1.240s	22.621us	50	50	100.00
V2	alert_test	kmac_alert_test	1.310s	22.708us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.440s	162.865us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.440s	162.865us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.390s	21.691us	5	5	100.00
		kmac_csr_rw	1.530s	145.622us	20	20	100.00
		kmac_csr_aliasing	7.660s	1.999ms	5	5	100.00
		kmac_same_csr_outstanding	3.400s	252.066us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.390s	21.691us	5	5	100.00
		kmac_csr_rw	1.530s	145.622us	20	20	100.00
		kmac_csr_aliasing	7.660s	1.999ms	5	5	100.00
		kmac_same_csr_outstanding	3.400s	252.066us	20	20	100.00
V2		TOTAL			738	740	99.73
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.980s	344.322us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.980s	344.322us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.980s	344.322us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.980s	344.322us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.490s	472.338us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.579m	17.145ms	5	5	100.00
		kmac_tl_intg_err	5.580s	232.109us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.580s	232.109us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	40.580s	678.816us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.457m	4.134ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.813m	19.879ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.980s	344.322us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.579m	17.145ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.579m	17.145ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.579m	17.145ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.457m	4.134ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	40.580s	678.816us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.579m	17.145ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.237m	36.008ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.457m	4.134ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.224m	21.120ms	8	10	80.00
V3		TOTAL			8	10	80.00
		TOTAL			936	940	99.57

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.33	99.27	94.45	99.76	80.99	97.15	97.83	97.86

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 2 failures:

  • Test kmac_stress_all_with_rand_reset has 2 failures.

    • 2.kmac_stress_all_with_rand_reset.111221923022871373240703205132347150075558899890694092186319819822915965829446
      Line 203, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4673080273 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 4673080273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 5.kmac_stress_all_with_rand_reset.43713462312160896752610199032850073080513419662954004096833442885268450513928
      Line 358, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 16567734082 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 16567734082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.err_code reset value: * has 1 failures:

  • Test kmac_key_error has 1 failures.

    • 14.kmac_key_error.30119784030156651681271424296902623736698925207450206004279478072845327817550
      Line 74, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_key_error/latest/run.log

        UVM_ERROR @ 1443303705 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 16777216 [0x1000000]) Regname: kmac_reg_block.err_code reset value: 0x0
        UVM_INFO @ 1443303705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test kmac_burst_write has 1 failures.

    • 20.kmac_burst_write.70201960282211892593121585376860893977976367625476755350741211421498138296976
      Line 255, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/20.kmac_burst_write/latest/run.log

        UVM_FATAL @ 500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---