OTBN Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 20.000s 87.144us 0 1 0.00
V1 single_binary otbn_single 53.000s 180.341us 0 100 0.00
V1 csr_hw_reset otbn_csr_hw_reset 5.000s 55.668us 5 5 100.00
V1 csr_rw otbn_csr_rw 5.000s 20.236us 20 20 100.00
V1 csr_bit_bash otbn_csr_bit_bash 7.000s 465.093us 5 5 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 20.596us 5 5 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 8.000s 41.825us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 5.000s 20.236us 20 20 100.00
otbn_csr_aliasing 4.000s 20.596us 5 5 100.00
V1 mem_walk otbn_mem_walk 35.000s 2.878ms 5 5 100.00
V1 mem_partial_access otbn_mem_partial_access 13.000s 429.173us 5 5 100.00
V1 TOTAL 65 166 39.16
V2 reset_recovery otbn_reset 53.000s 140.285us 0 10 0.00
V2 multi_error otbn_multi_err 47.000s 1.419ms 0 1 0.00
V2 back_to_back otbn_multi 1.483m 296.767us 0 10 0.00
V2 stress_all otbn_stress_all 1.533m 1.138ms 0 10 0.00
V2 lc_escalation otbn_escalate 18.000s 42.406us 25 60 41.67
V2 zero_state_err_urnd otbn_zero_state_err_urnd 8.000s 21.961us 2 5 40.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 35.000s 437.922us 0 10 0.00
V2 alert_test otbn_alert_test 7.000s 20.943us 50 50 100.00
V2 intr_test otbn_intr_test 7.000s 27.600us 50 50 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 12.000s 48.568us 20 20 100.00
V2 tl_d_illegal_access otbn_tl_errors 12.000s 48.568us 20 20 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 5.000s 55.668us 5 5 100.00
otbn_csr_rw 5.000s 20.236us 20 20 100.00
otbn_csr_aliasing 4.000s 20.596us 5 5 100.00
otbn_same_csr_outstanding 6.000s 31.271us 20 20 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 5.000s 55.668us 5 5 100.00
otbn_csr_rw 5.000s 20.236us 20 20 100.00
otbn_csr_aliasing 4.000s 20.596us 5 5 100.00
otbn_same_csr_outstanding 6.000s 31.271us 20 20 100.00
V2 TOTAL 167 246 67.89
V2S mem_integrity otbn_imem_err 13.000s 35.653us 0 10 0.00
otbn_dmem_err 11.000s 24.752us 0 15 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 13.000s 206.427us 0 5 0.00
otbn_controller_ispr_rdata_err 17.000s 61.566us 0 5 0.00
otbn_mac_bignum_acc_err 19.000s 80.930us 0 5 0.00
otbn_urnd_err 8.040s 0 2 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 9.000s 33.344us 5 5 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 6.000s 38.371us 2 2 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 9.000s 33.812us 8 10 80.00
V2S tl_intg_err otbn_sec_cm 3.967m 1.078ms 3 5 60.00
otbn_tl_intg_err 32.000s 812.759us 20 20 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 36.000s 239.158us 18 20 90.00
V2S prim_fsm_check otbn_sec_cm 3.967m 1.078ms 3 5 60.00
V2S prim_count_check otbn_sec_cm 3.967m 1.078ms 3 5 60.00
V2S sec_cm_mem_scramble otbn_smoke 20.000s 87.144us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 11.000s 24.752us 0 15 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 13.000s 35.653us 0 10 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 32.000s 812.759us 20 20 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 18.000s 42.406us 25 60 41.67
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 13.000s 35.653us 0 10 0.00
otbn_dmem_err 11.000s 24.752us 0 15 0.00
otbn_zero_state_err_urnd 8.000s 21.961us 2 5 40.00
otbn_illegal_mem_acc 9.000s 33.344us 5 5 100.00
otbn_sec_cm 3.967m 1.078ms 3 5 60.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 3.967m 1.078ms 3 5 60.00
V2S sec_cm_scramble_key_sideload otbn_single 53.000s 180.341us 0 100 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 13.000s 35.653us 0 10 0.00
otbn_dmem_err 11.000s 24.752us 0 15 0.00
otbn_zero_state_err_urnd 8.000s 21.961us 2 5 40.00
otbn_illegal_mem_acc 9.000s 33.344us 5 5 100.00
otbn_sec_cm 3.967m 1.078ms 3 5 60.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 3.967m 1.078ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 18.000s 42.406us 25 60 41.67
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 13.000s 35.653us 0 10 0.00
otbn_dmem_err 11.000s 24.752us 0 15 0.00
otbn_zero_state_err_urnd 8.000s 21.961us 2 5 40.00
otbn_illegal_mem_acc 9.000s 33.344us 5 5 100.00
otbn_sec_cm 3.967m 1.078ms 3 5 60.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 3.967m 1.078ms 3 5 60.00
V2S sec_cm_data_reg_sw_sca otbn_single 53.000s 180.341us 0 100 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 12.000s 46.634us 0 12 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 8.000s 23.438us 5 5 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 2.417m 686.014us 0 5 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 2.417m 686.014us 0 5 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 10.000s 27.412us 0 10 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 3.967m 1.078ms 3 5 60.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 3.967m 1.078ms 3 5 60.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 23.000s 76.072us 0 10 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 3.967m 1.078ms 3 5 60.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 3.967m 1.078ms 3 5 60.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 18.000s 212.424us 0 5 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 18.000s 212.424us 0 5 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 13.000s 20.051us 5 7 71.43
V2S sec_cm_data_mem_sec_wipe otbn_single 53.000s 180.341us 0 100 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 53.000s 180.341us 0 100 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 53.000s 180.341us 0 100 0.00
V2S sec_cm_write_mem_integrity otbn_multi 1.483m 296.767us 0 10 0.00
V2S sec_cm_ctrl_flow_count otbn_single 53.000s 180.341us 0 100 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 53.000s 180.341us 0 100 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 12.000s 25.090us 0 5 0.00
V2S sec_cm_key_sideload otbn_single 53.000s 180.341us 0 100 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 3.967m 1.078ms 3 5 60.00
V2S TOTAL 66 163 40.49
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 7.417m 3.495ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 298 585 50.94

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
93.73 97.76 71.18 96.97 77.53 58.03 87.18 80.11 98.72

Failure Buckets