8c9ab41| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 30.000s | 66.423us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 2.000s | 130.623us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 2.000s | 56.573us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 3.000s | 1.158ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 2.000s | 20.897us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 2.000s | 30.831us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 2.000s | 56.573us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 2.000s | 20.897us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 54.433m | 600.000ms | 23 | 50 | 46.00 |
| V2 | cnt_rollover | cnt_rollover | 1.567m | 5.371ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 30.000s | 19.507us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.763h | 2.687s | 24 | 50 | 48.00 |
| V2 | alert_test | pattgen_alert_test | 28.000s | 24.303us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 2.000s | 36.702us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 8.000s | 436.259us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 8.000s | 436.259us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 2.000s | 130.623us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 56.573us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 20.897us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 27.187us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 2.000s | 130.623us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 2.000s | 56.573us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 20.897us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 2.000s | 27.187us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 287 | 340 | 84.41 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 3.000s | 328.005us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 29.000s | 139.495us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 3.000s | 328.005us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.850m | 11.048ms | 2 | 50 | 4.00 |
| V3 | TOTAL | 2 | 50 | 4.00 | |||
| Unmapped tests | pattgen_inactive_level | 2.083m | 10.034ms | 34 | 50 | 68.00 | |
| TOTAL | 453 | 570 | 79.47 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.53 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 96.95 | 89.42 |
UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 48 failures:
0.pattgen_stress_all_with_rand_reset.110185051140689128709158493821652236703384280835890677675891095716593935872343
Line 110, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 218587946 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 218599509 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 218599509 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 218662008 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.114628748291989569393182150405776311198686092542122178692161216782035722840721
Line 130, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1772711692 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1772714184 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1772714184 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1772829570 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 46 more failures.
Job timed out after * minutes has 23 failures:
1.pattgen_perf.53523037794939105371325471060106272583211943451850054131353488432445501249262
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_perf/latest/run.log
Job timed out after 60 minutes
8.pattgen_perf.81879852063129942751100711700488807651248760323180143076731439232170645133046
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/8.pattgen_perf/latest/run.log
Job timed out after 60 minutes
... and 11 more failures.
3.pattgen_stress_all.79675826965287420874096479324677600609492657082127893548811417591935071071910
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/3.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
11.pattgen_stress_all.57096159218473398230148591844463216530001606720626201491096572721450256205088
Log /nightly/current_run/scratch/master/pattgen-sim-xcelium/11.pattgen_stress_all/latest/run.log
Job timed out after 180 minutes
... and 8 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 15 failures:
4.pattgen_stress_all.39486455555446903817713929080182751109398535719941891977606530132760254056384
Line 142, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/4.pattgen_stress_all/latest/run.log
UVM_ERROR @ 2835783897105 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10476
6.pattgen_stress_all.98032230844500145753013757940361015441835113077437091999688309236709036951907
Line 147, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/6.pattgen_stress_all/latest/run.log
UVM_ERROR @ 89697414108 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
-------------------------------------
Name Type Size Value
-------------------------------------
exp_item pattgen_item - @11022
... and 13 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 15 failures:
6.pattgen_perf.35314346109792242783015207478788675630355909034674673465676345137175254570006
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/6.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.pattgen_perf.95233558864279414069712376272756641960859084698219573774860920933945674847127
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/11.pattgen_perf/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
25.pattgen_stress_all.42861016210228662190907881648005615107159596330107029715467298148088767940763
Line 113, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/25.pattgen_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
28.pattgen_inactive_level.76210591238897086283746163103742462684344349983186158354381213147152709640953
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/28.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10015961318 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x50a23290, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10015961318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.pattgen_inactive_level.92290722165743146022974112403271497033129593805767990875763455456145823379791
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/40.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10099209407 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x64df0ed0, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10099209407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 2 failures:
31.pattgen_inactive_level.63377485420619322732012988130478969439308426415284591501208788002718372910074
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/31.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10128095089 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xc461aa10, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
UVM_INFO @ 10128095089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.pattgen_inactive_level.86462703275916554470971888150631099390297321468560533844820722867729665984329
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10149622101 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x4596a790, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
UVM_INFO @ 10149622101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) has 1 failures:
1.pattgen_inactive_level.115149753652226163808975778732297131569142915551648466470369675523823268962580
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10111551984 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x6876f410, Comparison=CompareOpEq, exp_data=0x0, call_count=24)
UVM_INFO @ 10111551984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
10.pattgen_inactive_level.84967421866515087685599322134373916193619271427946984387479341363643081496067
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10034436511 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5db14f10, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10034436511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
15.pattgen_inactive_level.58676982881204965599873479059767898601255608741436931143893514756376760997802
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10021506802 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc376a9d0, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10021506802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
22.pattgen_inactive_level.92436772906666681169138550796865049801758884473329178740581467866553742783265
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/22.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10098366603 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8707dcd0, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 10098366603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
26.pattgen_inactive_level.99038507839861795384729551374845352775314878729725127787415158960832562738617
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10041153312 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa8b0afd0, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
UVM_INFO @ 10041153312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
29.pattgen_inactive_level.11367137712404702701322327586343362076250340591045926408139176126346579258719
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/29.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10109868450 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x42e1a090, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
UVM_INFO @ 10109868450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
32.pattgen_inactive_level.43977234444516957557659279640457388422729375121847058409909181517313460330939
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/32.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10011251969 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x1315cf90, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
UVM_INFO @ 10011251969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
35.pattgen_inactive_level.88976276388637176642920583485332490279267847294757016783543175895399641958122
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/35.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10085197220 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x1eb33550, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 10085197220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
37.pattgen_inactive_level.2404692303971073068563015125178503252701060467399337676931221311940248033884
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/37.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10042057940 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x239fcf10, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
UVM_INFO @ 10042057940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
41.pattgen_inactive_level.43100303532600193052367697009339981165593600280451033816924863872330466817951
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/41.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10232690078 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc8b09490, Comparison=CompareOpEq, exp_data=0x0, call_count=27)
UVM_INFO @ 10232690078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
42.pattgen_inactive_level.40159768114657338793373584095673351262869787941871317950030261878245914579731
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/42.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10009492616 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xd4de3ad0, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10009492616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
46.pattgen_inactive_level.82386595135455985548587361384481501660296511955103975559830818093776474315210
Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/46.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 13066089811 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x58ddd510, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 13066089811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---