ROM_CTRL/32KB Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.190s	2.132ms	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.320s	126.252us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.140s	174.231us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.740s	177.511us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	7.980s	3.113ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.280s	183.790us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.140s	174.231us	20	20	100.00
		rom_ctrl_csr_aliasing	7.980s	3.113ms	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.160s	347.700us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.660s	168.210us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.390s	141.791us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	23.590s	2.220ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	8.190s	743.499us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	8.810s	1.077ms	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	11.460s	2.632ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	11.460s	2.632ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.320s	126.252us	5	5	100.00
		rom_ctrl_csr_rw	7.140s	174.231us	20	20	100.00
		rom_ctrl_csr_aliasing	7.980s	3.113ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	6.970s	171.754us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.320s	126.252us	5	5	100.00
		rom_ctrl_csr_rw	7.140s	174.231us	20	20	100.00
		rom_ctrl_csr_aliasing	7.980s	3.113ms	5	5	100.00
		rom_ctrl_same_csr_outstanding	6.970s	171.754us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.761m	12.724ms	17	20	85.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	27.560s	6.286ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.161m	879.620us	2	5	40.00
		rom_ctrl_tl_intg_err	1.051m	945.037us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.161m	879.620us	2	5	40.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.161m	879.620us	2	5	40.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.761m	12.724ms	17	20	85.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.761m	12.724ms	17	20	85.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.761m	12.724ms	17	20	85.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.761m	12.724ms	17	20	85.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.761m	12.724ms	17	20	85.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.161m	879.620us	2	5	40.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.161m	879.620us	2	5	40.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.190s	2.132ms	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.190s	2.132ms	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.190s	2.132ms	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.051m	945.037us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.761m	12.724ms	17	20	85.00
		rom_ctrl_kmac_err_chk	8.190s	743.499us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.761m	12.724ms	17	20	85.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.761m	12.724ms	17	20	85.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.761m	12.724ms	17	20	85.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	27.560s	6.286ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.161m	879.620us	2	5	40.00
V2S		TOTAL			59	65	90.77
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	6.631m	4.544ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			260	266	97.74

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.16	99.59	98.66	100.00	100.00	99.64	96.94	99.28

Failure Buckets

UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 3 failures:
- Test rom_ctrl_corrupt_sig_fatal_chk has 3 failures.
  - 5.rom_ctrl_corrupt_sig_fatal_chk.42649011948841614575037855017763824491577624160155331391302792610192593018879
    Line 98, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/5.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 1102461312 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 1102461312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 10.rom_ctrl_corrupt_sig_fatal_chk.34360004582100718847115255243622156829397415973382882148224050834206771609766
    Line 83, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/10.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log
```
  UVM_ERROR @ 380593998 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
  UVM_INFO @ 380593998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 2 failures:

Test rom_ctrl_sec_cm has 2 failures.

1.rom_ctrl_sec_cm.32860376778655940535198065112110464724016101396264324350664049945186298876337
Line 106, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 3003707ps failed at 3003707ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 3003707ps failed at 3003707ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

3.rom_ctrl_sec_cm.17289415116028752477497782277306521633397731675030923758602635994005348222647
Line 299, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 38968383ps failed at 38968383ps
      Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 38968383ps failed at 38968383ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

Test rom_ctrl_sec_cm has 1 failures.

4.rom_ctrl_sec_cm.74809682981455730620591276504523413129544018804789087329873703613832142486629
Line 105, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 8654382ps failed at 8654382ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 8779382ps failed at 8779382ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'