ROM_CTRL/64KB Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.590s	1.097ms	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	12.920s	218.439us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	11.050s	297.645us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	10.770s	287.330us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	10.530s	299.076us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	14.650s	4.136ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	11.050s	297.645us	20	20	100.00
		rom_ctrl_csr_aliasing	10.530s	299.076us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	9.510s	301.622us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	10.890s	420.574us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.690s	1.099ms	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	51.440s	17.183ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	16.160s	2.641ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	11.480s	289.922us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	15.420s	4.140ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	15.420s	4.140ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	12.920s	218.439us	5	5	100.00
		rom_ctrl_csr_rw	11.050s	297.645us	20	20	100.00
		rom_ctrl_csr_aliasing	10.530s	299.076us	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.290s	572.762us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	12.920s	218.439us	5	5	100.00
		rom_ctrl_csr_rw	11.050s	297.645us	20	20	100.00
		rom_ctrl_csr_aliasing	10.530s	299.076us	5	5	100.00
		rom_ctrl_same_csr_outstanding	15.290s	572.762us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.112m	27.895ms	20	20	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	1.176m	23.756ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	8.873m	1.082ms	0	5	0.00
		rom_ctrl_tl_intg_err	2.240m	888.506us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	8.873m	1.082ms	0	5	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	8.873m	1.082ms	0	5	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.112m	27.895ms	20	20	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.112m	27.895ms	20	20	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.112m	27.895ms	20	20	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.112m	27.895ms	20	20	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.112m	27.895ms	20	20	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	8.873m	1.082ms	0	5	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	8.873m	1.082ms	0	5	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.590s	1.097ms	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.590s	1.097ms	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.590s	1.097ms	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	2.240m	888.506us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.112m	27.895ms	20	20	100.00
		rom_ctrl_kmac_err_chk	16.160s	2.641ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.112m	27.895ms	20	20	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.112m	27.895ms	20	20	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.112m	27.895ms	20	20	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	1.176m	23.756ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	8.873m	1.082ms	0	5	0.00
V2S		TOTAL			60	65	92.31
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	3.592m	12.993ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			261	266	98.12

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.31	99.59	95.39	99.59	100.00	99.27	95.49	98.81

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 3 failures:

  • Test rom_ctrl_sec_cm has 3 failures.

    • 2.rom_ctrl_sec_cm.34941057553191308539364951076461521484110032735997606690466207236504511786365
      Line 240, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/2.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 26543520ps failed at 26543520ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 26543520ps failed at 26543520ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • 3.rom_ctrl_sec_cm.59970215889409576193394348573705908526162903985604160826314038088458391231902
      Line 289, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/3.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 40179209ps failed at 40179209ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 40179209ps failed at 40179209ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • ... and 1 more failures.

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.73542115389246763068871691030288392405700738300865671862492739685389611685320
      Line 689, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 290: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respOpcode_A: started at 476569068ps failed at 476569068ps
            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 476569068ps failed at 476569068ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
      

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:

  • Test rom_ctrl_sec_cm has 1 failures.

    • 1.rom_ctrl_sec_cm.75478904708914846382163911739894340899718572918910509078458607420289791226468
      Line 227, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/1.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 28099641ps failed at 28099641ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 35749563ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 35749563ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))