RV_TIMER Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.470s	394.888us	20	20	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.850s	18.666us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.910s	49.078us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.080s	292.120us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.940s	28.805us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.470s	64.561us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.910s	49.078us	20	20	100.00
		rv_timer_csr_aliasing	0.940s	28.805us	5	5	100.00
V1		TOTAL			75	75	100.00
V2	random_reset	rv_timer_random_reset	18.150s	29.350ms	2	20	10.00
V2	disabled	rv_timer_disabled	4.340s	2.851ms	20	20	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	19.723m	3.100s	10	10	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	19.723m	3.100s	10	10	100.00
V2	stress	rv_timer_stress_all	9.200s	6.744ms	20	20	100.00
V2	alert_test	rv_timer_alert_test	0.910s	12.440us	50	50	100.00
V2	intr_test	rv_timer_intr_test	0.870s	16.310us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.920s	1.719ms	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.920s	1.719ms	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.850s	18.666us	5	5	100.00
		rv_timer_csr_rw	0.910s	49.078us	20	20	100.00
		rv_timer_csr_aliasing	0.940s	28.805us	5	5	100.00
		rv_timer_same_csr_outstanding	1.190s	36.917us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.850s	18.666us	5	5	100.00
		rv_timer_csr_rw	0.910s	49.078us	20	20	100.00
		rv_timer_csr_aliasing	0.940s	28.805us	5	5	100.00
		rv_timer_same_csr_outstanding	1.190s	36.917us	20	20	100.00
V2		TOTAL			192	210	91.43
V2S	tl_intg_err	rv_timer_sec_cm	1.270s	200.215us	5	5	100.00
		rv_timer_tl_intg_err	1.500s	3.259ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.500s	3.259ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	min_value	rv_timer_min	1.600s	205.205us	4	10	40.00
V3	max_value	rv_timer_max	1.760s	349.709us	0	10	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	43.790s	5.704ms	16	20	80.00
V3		TOTAL			20	40	50.00
		TOTAL			312	350	89.14

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.77	100.00	100.00	78.66	--	100.00	96.82	99.12

Failure Buckets

UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 24 failures:
- Test rv_timer_min has 6 failures.
  - 0.rv_timer_min.88460464999585664360870094539829880100638021427297505343800522251199154796759
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 276953713 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe3292904) == 0x1
  UVM_INFO @ 276953713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.rv_timer_min.52053570214851496081126145785798042566555468731894704184334643832368263559228
    Line 75, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/2.rv_timer_min/latest/run.log
```
  UVM_FATAL @ 284488200 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8f790704) == 0x1
  UVM_INFO @ 284488200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
- Test rv_timer_random_reset has 18 failures.
  - 0.rv_timer_random_reset.64545968177383789324830477327923534777379663748898695595012128860458735263646
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @  79376908 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x456bab04) == 0x1
  UVM_INFO @  79376908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_random_reset.46549287380866364590690926979730130310410005816271116425115397741841014888401
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_random_reset/latest/run.log
```
  UVM_FATAL @ 13311082769 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe8f93104) == 0x1
  UVM_INFO @ 13311082769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 16 more failures.
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 10 failures:
- Test rv_timer_max has 10 failures.
  - 0.rv_timer_max.113267353156603988057058741118660711038049615066520292811524653371974643068612
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
```
  UVM_ERROR @  88633065 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @  88633065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_max.7248147091716587247226868425921248640650813566103628614284574818841226871781
    Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log
```
  UVM_ERROR @ 334776692 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 334776692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test rv_timer_stress_all_with_rand_reset has 2 failures.

3.rv_timer_stress_all_with_rand_reset.16678106825132059265307125939464373370934349798779827680506788454923342023080
Line 395, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 44292173618 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 44292173618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.rv_timer_stress_all_with_rand_reset.104692164096022589584823091370839415430629094832653499564336183193436699068154
Line 236, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9477207963 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 9477207963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 2 failures:
- Test rv_timer_stress_all_with_rand_reset has 2 failures.
  - 14.rv_timer_stress_all_with_rand_reset.21551219549367499930340055517397082343730832815352798627452828422298677506055
    Line 220, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/14.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 13350214217 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 13350214217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 15.rv_timer_stress_all_with_rand_reset.14363403388899637525150049079789011050560702977118831078007548200681040880355
    Line 86, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/15.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 254135024 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
  UVM_INFO @ 254135024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```