SPI_DEVICE/1R1W Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.140m	296.563ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.690s	24.610us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.050s	117.233us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	29.350s	12.879ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.630s	634.547us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.700s	154.014us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.050s	117.233us	20	20	100.00
		spi_device_csr_aliasing	15.630s	634.547us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	1.030s	21.793us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.470s	113.228us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.220s	42.236us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.080s	2.766us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.060s	3.106us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	10.090s	988.417us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.090s	988.417us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	24.480s	35.304ms	50	50	100.00
		spi_device_tpm_sts_read	1.490s	118.182us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	45.220s	44.171ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	31.990s	62.592ms	50	50	100.00
		spi_device_flash_all	5.804m	77.302ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	46.750s	52.827ms	50	50	100.00
		spi_device_flash_all	5.804m	77.302ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	46.750s	52.827ms	50	50	100.00
		spi_device_flash_all	5.804m	77.302ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.804m	77.302ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	23.520s	21.011ms	50	50	100.00
		spi_device_flash_all	5.804m	77.302ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	23.520s	21.011ms	50	50	100.00
		spi_device_flash_all	5.804m	77.302ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	23.520s	21.011ms	50	50	100.00
		spi_device_flash_all	5.804m	77.302ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	23.520s	21.011ms	50	50	100.00
		spi_device_flash_all	5.804m	77.302ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	23.520s	21.011ms	50	50	100.00
		spi_device_flash_all	5.804m	77.302ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	31.680s	39.967ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.496m	54.179ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.496m	54.179ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.496m	54.179ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	46.380s	7.277ms	50	50	100.00
		spi_device_read_buffer_direct	19.390s	2.727ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.496m	54.179ms	50	50	100.00
		spi_device_flash_all	5.804m	77.302ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.804m	77.302ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.804m	77.302ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	28.780s	4.897ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	28.780s	4.897ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.140m	296.563ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	6.628m	224.672ms	50	50	100.00
V2	stress_all	spi_device_stress_all	14.572m	122.864ms	49	50	98.00
V2	alert_test	spi_device_alert_test	1.140s	25.759us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.130s	34.222us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.670s	896.196us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.670s	896.196us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.690s	24.610us	5	5	100.00
		spi_device_csr_rw	3.050s	117.233us	20	20	100.00
		spi_device_csr_aliasing	15.630s	634.547us	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	191.960us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.690s	24.610us	5	5	100.00
		spi_device_csr_rw	3.050s	117.233us	20	20	100.00
		spi_device_csr_aliasing	15.630s	634.547us	5	5	100.00
		spi_device_same_csr_outstanding	4.570s	191.960us	20	20	100.00
V2		TOTAL			939	961	97.71
V2S	tl_intg_err	spi_device_sec_cm	1.510s	66.271us	5	5	100.00
		spi_device_tl_intg_err	21.910s	1.046ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	21.910s	1.046ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	51.207m	1.500s	49	50	98.00
		TOTAL			1128	1151	98.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.61	99.11	96.56	71.19	89.36	98.40	94.43	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.13080632912231529175438643553166437161497255072852404118109307361927000863378
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1085491 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[47])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1085491 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1085491 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[943])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.14289244902052274889946974205453397125725840800975995730571432895539981486471
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2220781 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[83])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2220781 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2220781 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[979])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.35866159346912827523210945370262402090460647157878202860626026402022649806970
Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @    797079 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x779dde [11101111001110111011110] vs 0x0 [0])
  UVM_ERROR @    853079 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb749c3 [101101110100100111000011] vs 0x0 [0])
  UVM_ERROR @    920079 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x91bc5b [100100011011110001011011] vs 0x0 [0])
  UVM_ERROR @    934079 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xccd404 [110011001101010000000100] vs 0x0 [0])
  UVM_ERROR @   1023079 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x934ebe [100100110100111010111110] vs 0x0 [0])

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 15.spi_device_flash_mode_ignore_cmds.1245812066360151112055795325413213562974316524097915386192928406957551283943
    Line 102, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  UVM_FATAL @ 1500000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1500000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test spi_device_stress_all has 1 failures.
  - 48.spi_device_stress_all.7762057549509848894266118138790572007918655761873434598409567072993161166362
    Log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/48.spi_device_stress_all/latest/run.log
```
  Job timed out after 180 minutes
```