SPI_DEVICE/2P Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	5.756m	105.400ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.540s	456.002us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.860s	479.162us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	19.060s	8.175ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.820s	320.941us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.040s	296.245us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.860s	479.162us	20	20	100.00
		spi_device_csr_aliasing	16.820s	320.941us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.990s	27.888us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.340s	278.442us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	1.200s	38.908us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.520s	77.194us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.030s	46.669us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	7.180s	253.109us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	7.180s	253.109us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	30.230s	9.563ms	50	50	100.00
		spi_device_tpm_sts_read	1.410s	86.935us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	43.600s	9.709ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	28.870s	17.264ms	50	50	100.00
		spi_device_flash_all	7.041m	85.538ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	25.760s	8.192ms	50	50	100.00
		spi_device_flash_all	7.041m	85.538ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	25.760s	8.192ms	50	50	100.00
		spi_device_flash_all	7.041m	85.538ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	7.041m	85.538ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	25.020s	2.301ms	50	50	100.00
		spi_device_flash_all	7.041m	85.538ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	25.020s	2.301ms	50	50	100.00
		spi_device_flash_all	7.041m	85.538ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	25.020s	2.301ms	50	50	100.00
		spi_device_flash_all	7.041m	85.538ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	25.020s	2.301ms	50	50	100.00
		spi_device_flash_all	7.041m	85.538ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	25.020s	2.301ms	50	50	100.00
		spi_device_flash_all	7.041m	85.538ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	46.330s	18.243ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.764m	35.436ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.764m	35.436ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.764m	35.436ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	49.500s	7.113ms	50	50	100.00
		spi_device_read_buffer_direct	17.950s	1.704ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.764m	35.436ms	50	50	100.00
		spi_device_flash_all	7.041m	85.538ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	7.041m	85.538ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	7.041m	85.538ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	21.680s	6.865ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	21.680s	6.865ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	5.756m	105.400ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	5.532m	67.171ms	50	50	100.00
V2	stress_all	spi_device_stress_all	13.092m	118.234ms	50	50	100.00
V2	alert_test	spi_device_alert_test	1.130s	28.052us	50	50	100.00
V2	intr_test	spi_device_intr_test	1.020s	14.085us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.630s	81.397us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.630s	81.397us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.540s	456.002us	5	5	100.00
		spi_device_csr_rw	2.860s	479.162us	20	20	100.00
		spi_device_csr_aliasing	16.820s	320.941us	5	5	100.00
		spi_device_same_csr_outstanding	3.950s	178.220us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.540s	456.002us	5	5	100.00
		spi_device_csr_rw	2.860s	479.162us	20	20	100.00
		spi_device_csr_aliasing	16.820s	320.941us	5	5	100.00
		spi_device_same_csr_outstanding	3.950s	178.220us	20	20	100.00
V2		TOTAL			961	961	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.580s	250.088us	5	5	100.00
		spi_device_tl_intg_err	18.260s	1.114ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.260s	1.114ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.381m	536.682ms	49	50	98.00
		TOTAL			1150	1151	99.91

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.16	99.17	96.65	74.78	89.36	98.51	94.41	99.26

Failure Buckets

• UVM_ERROR (spi_device_pass_base_vseq.sv:705) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [*] vs * [*]) flash_status.busy == * expected to be * has 1 failures:
  • Test spi_device_flash_mode_ignore_cmds has 1 failures.

    • 37.spi_device_flash_mode_ignore_cmds.41757146721332127621798249234989098636424292466230843892574004610830735536858
      Line 95, in log /nightly/current_run/scratch/master/spi_device_2p-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest/run.log

        UVM_ERROR @ 10375906142 ps: (spi_device_pass_base_vseq.sv:705) [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == 0 (1 [0x1] vs 0 [0x0]) flash_status.busy == 1 expected to be 0
        UVM_INFO @ 11412844660 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 3/7
        UVM_INFO @ 11412844660 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 4/7
        UVM_INFO @ 12754870022 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 4/7
        UVM_INFO @ 12754870022 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 5/7