SPI_HOST Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.650m	23.314ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	18.386us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	53.920us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	4.000s	158.692us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	25.041us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	481.556us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	53.920us	20	20	100.00
		spi_host_csr_aliasing	2.000s	25.041us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	40.029us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	31.338us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	3.000s	229.616us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	28.000s	2.157ms	50	50	100.00
		spi_host_error_cmd	2.000s	18.389us	50	50	100.00
		spi_host_event	6.567m	53.687ms	50	50	100.00
V2	clock_rate	spi_host_speed	8.000s	1.339ms	50	50	100.00
V2	speed	spi_host_speed	8.000s	1.339ms	50	50	100.00
V2	chip_select_timing	spi_host_speed	8.000s	1.339ms	50	50	100.00
V2	sw_reset	spi_host_sw_reset	1.717m	3.936ms	50	50	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	57.018us	50	50	100.00
V2	cpol_cpha	spi_host_speed	8.000s	1.339ms	50	50	100.00
V2	full_cycle	spi_host_speed	8.000s	1.339ms	50	50	100.00
V2	duplex	spi_host_smoke	1.650m	23.314ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	1.650m	23.314ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.733m	2.989ms	50	50	100.00
V2	spien	spi_host_spien	3.883m	14.711ms	49	50	98.00
V2	stall	spi_host_status_stall	39.617m	869.238ms	49	50	98.00
V2	Idlecsbactive	spi_host_idlecsbactive	48.000s	2.716ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	28.000s	2.157ms	50	50	100.00
V2	alert_test	spi_host_alert_test	2.000s	23.560us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	19.994us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	152.080us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	152.080us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	18.386us	5	5	100.00
		spi_host_csr_rw	3.000s	53.920us	20	20	100.00
		spi_host_csr_aliasing	2.000s	25.041us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	51.056us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	18.386us	5	5	100.00
		spi_host_csr_rw	3.000s	53.920us	20	20	100.00
		spi_host_csr_aliasing	2.000s	25.041us	5	5	100.00
		spi_host_same_csr_outstanding	2.000s	51.056us	20	20	100.00
V2		TOTAL			688	690	99.71
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	74.704us	20	20	100.00
		spi_host_sec_cm	2.000s	793.432us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	74.704us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	8.417m	42.462ms	10	10	100.00
		TOTAL			838	840	99.76

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.12	96.87	93.45	98.69	94.25	73.07	100.00	95.21	90.42

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 14.spi_host_status_stall.83136846370436820287368786408580137340444636223052294521339131117487255611464
      Line 3344, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/14.spi_host_status_stall/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/spi_host-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 7730139012 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
        UVM_ERROR @ 7730139012 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=7730139000 ps
        UVM_INFO @ 7730139012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:

  • Test spi_host_spien has 1 failures.

    • 36.spi_host_spien.34692503081439305744092995030923062420019508634598274563049406180760854943479
      Line 310, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/36.spi_host_spien/latest/run.log

        UVM_FATAL @ 10549259514 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x7bcb5b54, Comparison=CompareOpEq, exp_data=0x0, call_count=47
        UVM_INFO @ 10549259514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---