SRAM_CTRL/MAIN Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: 8c9ab41

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.734m	2.588ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.100s	114.394us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.060s	13.518us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.550s	464.045us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.030s	22.943us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.600s	1.832ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.060s	13.518us	20	20	100.00
		sram_ctrl_csr_aliasing	1.030s	22.943us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.268m	41.400ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.013m	11.049ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	22.878m	35.779ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.077m	12.693ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	38.233m	172.637ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	21.092m	19.996ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.858m	222.222ms	50	50	100.00
V2	executable	sram_ctrl_executable	21.451m	31.922ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	2.018m	5.854ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.063m	27.950ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.775m	9.512ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.760m	1.597ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.598m	3.714ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	23.006m	36.378ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	6.350s	4.172ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.982h	324.692ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.080s	133.381us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.710s	157.257us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.710s	157.257us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.100s	114.394us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	13.518us	20	20	100.00
		sram_ctrl_csr_aliasing	1.030s	22.943us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.220s	29.273us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.100s	114.394us	5	5	100.00
		sram_ctrl_csr_rw	1.060s	13.518us	20	20	100.00
		sram_ctrl_csr_aliasing	1.030s	22.943us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.220s	29.273us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.163m	9.542ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.980s	3.355us	0	5	0.00
		sram_ctrl_tl_intg_err	3.820s	615.556us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.980s	3.355us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.820s	615.556us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	23.006m	36.378ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	23.006m	36.378ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.060s	13.518us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	21.451m	31.922ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	21.451m	31.922ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	21.451m	31.922ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.858m	222.222ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	10.010s	5.118ms	40	50	80.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.163m	9.542ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	12.620s	9.473ms	35	50	70.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.734m	2.588ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.734m	2.588ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	21.451m	31.922ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.980s	3.355us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.858m	222.222ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.980s	3.355us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.980s	3.355us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.734m	2.588ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.980s	3.355us	0	5	0.00
V2S		TOTAL			115	145	79.31
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	7.312m	13.807ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1160	1190	97.48

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.66	99.11	92.90	85.46	100.00	98.02	95.83	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 15 failures:

  • Test sram_ctrl_readback_err has 15 failures.

    • 0.sram_ctrl_readback_err.9387847605787655820305005514747412341355569466209890303798731344347583786050
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 685998977 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2e) != exp (0x1a)
        UVM_INFO @ 685998977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_readback_err.74019880720855343175064872452307455163860476765633130345065731975571307771756
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 657766623 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x5d) != exp (0x14)
        UVM_INFO @ 657766623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 13 more failures.

• Offending 'reqfifo_rvalid' has 10 failures:

  • Test sram_ctrl_mubi_enc_err has 10 failures.

    • 4.sram_ctrl_mubi_enc_err.98791474148469212355302593209298483870048948213563352673311826640519822806345
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1551092060 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1551092060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.sram_ctrl_mubi_enc_err.73349854861686152007692400864970511161237534980206314462935998083373563241524
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/6.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 1351882512 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 1351882512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 0.sram_ctrl_sec_cm.115408809380108729579343154802127980682351200393615180157679385584734327784244
      Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  20403333 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  20403333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.105556898523107474566672270394734362143497121922811212268930672175179425645674
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2512741 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2512741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 2 failures:

  • Test sram_ctrl_sec_cm has 2 failures.

    • 3.sram_ctrl_sec_cm.79072870567202027200427883773564721912744748038384293940827775465367067663518
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   3354993 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3354993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.sram_ctrl_sec_cm.44737261360689683763907354679592418307413700674847037753301928944170603449181
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   2136011 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   2136011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 1.sram_ctrl_sec_cm.86999339972676163196559048018593556213712651092129497790769780182883723339450
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   2148223 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   2148223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---