SRAM_CTRL/RET Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.731m	4.125ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.080s	16.926us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.110s	160.631us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.730s	362.003us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.120s	143.500us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.640s	89.336us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.110s	160.631us	20	20	100.00
		sram_ctrl_csr_aliasing	1.120s	143.500us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	13.250s	467.274us	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.880s	349.514us	50	50	100.00
V1		TOTAL			203	205	99.02
V2	multiple_keys	sram_ctrl_multiple_keys	20.192m	11.851ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.398m	4.388ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.428m	21.617ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	19.263m	4.368ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	13.790s	3.917ms	50	50	100.00
V2	executable	sram_ctrl_executable	26.174m	81.812ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.716m	214.426us	50	50	100.00
		sram_ctrl_partial_access_b2b	10.063m	132.388ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.628m	1.286ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.786m	157.907us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.769m	455.065us	50	50	100.00
V2	regwen	sram_ctrl_regwen	20.555m	15.522ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.210s	36.143us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.247h	269.944ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	1.080s	17.154us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.460s	543.286us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.460s	543.286us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.080s	16.926us	5	5	100.00
		sram_ctrl_csr_rw	1.110s	160.631us	20	20	100.00
		sram_ctrl_csr_aliasing	1.120s	143.500us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.240s	233.439us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.080s	16.926us	5	5	100.00
		sram_ctrl_csr_rw	1.110s	160.631us	20	20	100.00
		sram_ctrl_csr_aliasing	1.120s	143.500us	5	5	100.00
		sram_ctrl_same_csr_outstanding	1.240s	233.439us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.690s	2.805ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.160s	31.516us	0	5	0.00
		sram_ctrl_tl_intg_err	4.070s	490.739us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.160s	31.516us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.070s	490.739us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	20.555m	15.522ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	20.555m	15.522ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.110s	160.631us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	26.174m	81.812ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	26.174m	81.812ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	26.174m	81.812ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	13.790s	3.917ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.680s	52.335us	47	50	94.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.690s	2.805ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.480s	272.554us	41	50	82.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.731m	4.125ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.731m	4.125ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	26.174m	81.812ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.160s	31.516us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	13.790s	3.917ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.160s	31.516us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.160s	31.516us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.731m	4.125ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.160s	31.516us	0	5	0.00
V2S		TOTAL			128	145	88.28
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	9.599m	2.375ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1170	1190	98.32

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.64	99.07	92.90	85.37	100.00	97.98	95.79	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 9 failures:
- Test sram_ctrl_readback_err has 9 failures.
  - 4.sram_ctrl_readback_err.100547183702584332756954126174201367670592176995852704597275365655483389123315
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  23642054 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x57) != exp (0x11)
  UVM_INFO @  23642054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.sram_ctrl_readback_err.36895228173207938312745831499271549094966129470432036006197178160554450586547
    Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/9.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  32862037 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x79) != exp (0x7)
  UVM_INFO @  32862037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

Test sram_ctrl_sec_cm has 3 failures.

0.sram_ctrl_sec_cm.8255321135179045112353913681492975643798985208736034508083448482067839802735
Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @   5024882 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   5024882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.sram_ctrl_sec_cm.52793513544611992242817397937883983701123014755216851299430207718533598978870
Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

  UVM_ERROR @  31516135 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @  31516135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Offending 'reqfifo_rvalid' has 3 failures:
- Test sram_ctrl_mubi_enc_err has 3 failures.
  - 11.sram_ctrl_mubi_enc_err.69501285911686297179121641099493898793486402582691607648508797333457893409285
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/11.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  32788536 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  32788536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 17.sram_ctrl_mubi_enc_err.86567894220508200827672848358626743343369829769450435063179695621742495402598
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/17.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 138670120 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 138670120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:

Test sram_ctrl_sec_cm has 1 failures.

1.sram_ctrl_sec_cm.37042767452006185917475793822909642829608406573646705319656459808040138023136
Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  UVM_ERROR @   2986540 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   2986540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(depth_o <= *'(Depth))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 2.sram_ctrl_sec_cm.48695117806222973141851237152621469496632491145363326439558797882034003463183
    Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(depth_o <= 2'(Depth))'
  UVM_ERROR @   6867718 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
  UVM_INFO @   6867718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 7.sram_ctrl_csr_mem_rw_with_rand_reset.47823898598364771076210613949383367426561356223965071618080947024927911147494
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 171945378 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (4 [0x4] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @ 171945378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 17.sram_ctrl_csr_mem_rw_with_rand_reset.7920452022660257680249770052686630836666620316296524847512199955498352606994
    Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 100666356 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (40 [0x28] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @ 100666356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1229) [sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 44.sram_ctrl_stress_all_with_rand_reset.4462429285081996205836974494320052828514921933293553102976013822178225190174
    Line 311, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/44.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2417647095 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 75000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2417647095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```