CHIP Simulation Results

Sunday October 19 2025 00:12:47 UTC

GitHub Revision: `8c9ab41`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	3.397m	3.378ms	3	3	100.00
		chip_sw_example_rom	1.602m	2.112ms	3	3	100.00
		chip_sw_example_manufacturer	2.934m	3.070ms	3	3	100.00
		chip_sw_example_concurrency	3.469m	3.000ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	5.054m	6.266ms	5	5	100.00
V1	csr_rw	chip_csr_rw	9.273m	5.642ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.296h	59.045ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	1.320h	32.732ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	13.034m	9.338ms	9	20	45.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.320h	32.732ms	5	5	100.00
		chip_csr_rw	9.273m	5.642ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	10.810s	250.157us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.268m	4.728ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.268m	4.728ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.268m	4.728ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	8.366m	4.455ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	8.366m	4.455ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	8.833m	4.681ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	8.040m	3.977ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	8.861m	4.523ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	35.328m	13.424ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	22.148m	8.777ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	24.656m	13.081ms	5	5	100.00
V1		TOTAL			209	220	95.00
V2	chip_pin_mux	chip_padctrl_attributes	3.444m	5.785ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.444m	5.785ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	4.678m	3.246ms	1	3	33.33
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	6.758m	6.841ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	4.109m	3.505ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	19.632m	14.235ms	5	5	100.00
		chip_tap_straps_testunlock0	9.734m	7.676ms	5	5	100.00
		chip_tap_straps_rma	11.241m	8.154ms	5	5	100.00
		chip_tap_straps_prod	18.587m	14.260ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.254m	3.132ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	17.734m	9.820ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	9.165m	4.929ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	9.165m	4.929ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.200m	7.766ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	1.075h	23.335ms	2	3	66.67
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	7.821m	4.097ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	12.932m	5.441ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.260h	19.452ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.423m	3.098ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	14.202m	6.966ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	3.631m	3.752ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	32.349m	12.529ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	4.481m	3.452ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.872m	5.276ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.339m	2.207ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.389m	3.019ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	14.517m	8.831ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	6.154m	5.749ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	3.537m	3.019ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	6.154m	5.749ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	3.657m	2.797ms	3	3	100.00
		chip_sw_aes_smoketest	4.203m	2.933ms	3	3	100.00
		chip_sw_aon_timer_smoketest	3.750m	3.624ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.136m	3.158ms	3	3	100.00
		chip_sw_csrng_smoketest	3.536m	2.859ms	3	3	100.00
		chip_sw_entropy_src_smoketest	18.243m	6.761ms	3	3	100.00
		chip_sw_gpio_smoketest	4.263m	2.780ms	3	3	100.00
		chip_sw_hmac_smoketest	4.103m	3.528ms	3	3	100.00
		chip_sw_kmac_smoketest	4.439m	3.433ms	3	3	100.00
		chip_sw_otbn_smoketest	35.842m	11.556ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	5.735m	5.585ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	6.600m	6.764ms	3	3	100.00
		chip_sw_rv_plic_smoketest	3.251m	2.658ms	3	3	100.00
		chip_sw_rv_timer_smoketest	3.729m	2.799ms	3	3	100.00
		chip_sw_rstmgr_smoketest	3.889m	3.060ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	3.583m	3.252ms	3	3	100.00
		chip_sw_uart_smoketest	3.092m	2.467ms	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	3.718m	3.146ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	8.104m	5.173ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.416h	60.246ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	1.026h	14.681ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	17.720m	15.200ms	2	3	66.67
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	4.023m	3.332ms	0	3	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	4.326m	3.353ms	0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.094h	53.348ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.261h	57.093ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.910m	3.601ms	3	30	10.00
V2	tl_d_illegal_access	chip_tl_errors	3.910m	3.601ms	3	30	10.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.320h	32.732ms	5	5	100.00
		chip_same_csr_outstanding	55.736m	27.229ms	20	20	100.00
		chip_csr_hw_reset	5.054m	6.266ms	5	5	100.00
		chip_csr_rw	9.273m	5.642ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.320h	32.732ms	5	5	100.00
		chip_same_csr_outstanding	55.736m	27.229ms	20	20	100.00
		chip_csr_hw_reset	5.054m	6.266ms	5	5	100.00
		chip_csr_rw	9.273m	5.642ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.417m	2.396ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.830s	51.613us	100	100	100.00
		xbar_smoke_large_delays	2.016m	10.289ms	100	100	100.00
		xbar_smoke_slow_rsp	1.612m	6.057ms	100	100	100.00
		xbar_random_zero_delays	48.140s	552.468us	100	100	100.00
		xbar_random_large_delays	8.281m	56.307ms	100	100	100.00
		xbar_random_slow_rsp	6.295m	33.844ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	54.330s	1.433ms	100	100	100.00
		xbar_error_and_unmapped_addr	52.370s	1.378ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.298m	2.329ms	100	100	100.00
		xbar_error_and_unmapped_addr	52.370s	1.378ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.853m	2.669ms	100	100	100.00
		xbar_access_same_device_slow_rsp	14.895m	88.449ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.157m	2.520ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	7.281m	14.936ms	100	100	100.00
		xbar_stress_all_with_error	8.155m	20.341ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	12.837m	11.382ms	100	100	100.00
		xbar_stress_all_with_reset_error	10.273m	9.705ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.026h	14.681ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	58.611m	29.669ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.037h	14.827ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	42.602m	11.117ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	1.003h	16.019ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	1.022h	16.412ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	1.034h	17.831ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	58.383m	14.650ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	24.460s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	28.540s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	21.990s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	18.940s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	24.530s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.970s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	18.070s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	23.740s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.300s	10.180us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	20.420s	10.360us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	23.660s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	18.990s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.080s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	17.330s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	17.300s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	18.650s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	18.550s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	20.980s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	17.990s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	20.640s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.210s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	19.300s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	29.020s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	25.050s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	22.720s	10.100us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	47.322m	12.246ms	3	3	100.00
		rom_e2e_asm_init_dev	1.034h	16.887ms	3	3	100.00
		rom_e2e_asm_init_prod	1.050h	15.905ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.048h	15.260ms	3	3	100.00
		rom_e2e_asm_init_rma	1.016h	15.475ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	1.014h	15.448ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.018h	15.073ms	3	3	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	59.523m	14.825ms	3	3	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.080h	15.590ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	3	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.609m	2.953ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.423m	3.098ms	3	3	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.377m	2.959ms	3	3	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.326m	2.750ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	23.873m	9.716ms	3	3	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.060m	3.369ms	0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	8.093m	6.336ms	3	3	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	10.087m	6.030ms	95	100	95.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	12.147m	6.226ms	3	3	100.00
		chip_plic_all_irqs_10	5.986m	4.067ms	3	3	100.00
		chip_plic_all_irqs_20	8.590m	3.866ms	3	3	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	4.412m	3.262ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	22.235m	12.908ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	8.677m	5.213ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	3.686m	2.912ms	0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	25.672m	8.959ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	24.525m	9.123ms	3	3	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	17.350m	8.033ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.237h	255.960ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	5.791m	4.273ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	5.735m	5.585ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	5.791m	4.273ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	11.729m	9.876ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	11.729m	9.876ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.359m	7.512ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	7.980m	5.080ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	12.495m	6.296ms	3	3	100.00
		chip_sw_aes_idle	3.326m	2.750ms	3	3	100.00
		chip_sw_hmac_enc_idle	3.658m	3.210ms	3	3	100.00
		chip_sw_kmac_idle	2.852m	2.730ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	5.291m	4.089ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	6.873m	4.762ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	6.819m	4.471ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	6.709m	4.735ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	16.190m	10.396ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	8.347m	3.809ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	8.747m	4.852ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	7.714m	3.936ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	8.436m	4.288ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	8.134m	4.027ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	7.658m	4.572ms	3	3	100.00
		chip_sw_ast_clk_outputs	12.200m	7.766ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.895m	12.364ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	7.714m	3.936ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	8.436m	4.288ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	7.821m	4.097ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	12.932m	5.441ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.260h	19.452ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	3.423m	3.098ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	14.202m	6.966ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	3.631m	3.752ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	32.349m	12.529ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	4.481m	3.452ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.872m	5.276ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.339m	2.207ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.877m	3.078ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	8.545m	4.881ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	14.375m	7.498ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.282h	25.017ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	3.246m	3.161ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	3.611m	3.217ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	27.258m	12.195ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	3.187m	2.657ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	7.936m	5.490ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	26.636m	21.407ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	4.758h	144.133ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.200m	7.766ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	8.791m	4.650ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	6.109m	3.800ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	10.087m	6.030ms	95	100	95.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	25.672m	8.959ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	24.262m	8.290ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	7.122m	5.006ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	10.930m	7.542ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.713m	2.732ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.537h	24.568ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	3.148m	3.417ms	3	3	100.00
		chip_sw_edn_entropy_reqs	15.897m	7.836ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	3.148m	3.417ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	24.262m	8.290ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	3.496m	2.911ms	3	3	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	30.794m	19.066ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	12.962m	5.331ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	12.932m	5.441ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	6.895m	3.603ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	7.821m	4.097ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.275h	43.191ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	30.794m	19.066ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	4.315m	3.774ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	34.859m	11.914ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	6.984m	4.932ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.275h	43.191ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	6.984m	4.932ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	6.984m	4.932ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	6.984m	4.932ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	6.984m	4.932ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	10.087m	6.030ms	95	100	95.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	11.304m	14.838ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	10.495m	5.518ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	8.736m	5.969ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	8.736m	5.969ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.974m	2.926ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	3.631m	3.752ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.658m	3.210ms	3	3	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	3.832m	3.308ms	0	3	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	7.484m	3.452ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	9.821m	5.302ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	8.671m	5.108ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	8.571m	5.481ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	6.595m	4.137ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	34.859m	11.914ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	32.349m	12.529ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	33.334m	10.825ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	23.873m	9.716ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	56.673m	14.867ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.889m	3.149ms	3	3	100.00
		chip_sw_kmac_mode_kmac	4.861m	3.499ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	4.481m	3.452ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	34.859m	11.914ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	14.796m	9.821ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.003m	3.248ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	30.151m	9.873ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.852m	2.730ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	8.093m	6.336ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	19.632m	14.235ms	5	5	100.00
		chip_tap_straps_rma	11.241m	8.154ms	5	5	100.00
		chip_tap_straps_prod	18.587m	14.260ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.036m	3.313ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	14.796m	9.821ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	14.796m	9.821ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	14.796m	9.821ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	37.198m	12.247ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	6.984m	4.932ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.275h	43.191ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.929m	3.700ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	11.845m	8.003ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	13.604m	6.649ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	12.192m	6.635ms	0	3	0.00
		chip_sw_lc_ctrl_transition	14.796m	9.821ms	15	15	100.00
		chip_sw_keymgr_key_derivation	34.859m	11.914ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	8.211m	9.789ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	9.714m	7.194ms	3	3	100.00
		chip_prim_tl_access	11.304m	14.838ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.895m	12.364ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	8.347m	3.809ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	8.747m	4.852ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	7.714m	3.936ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	8.436m	4.288ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	8.134m	4.027ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	7.658m	4.572ms	3	3	100.00
		chip_tap_straps_dev	19.632m	14.235ms	5	5	100.00
		chip_tap_straps_rma	11.241m	8.154ms	5	5	100.00
		chip_tap_straps_prod	18.587m	14.260ms	5	5	100.00
		chip_rv_dm_lc_disabled	7.663m	14.114ms	0	3	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.072m	3.593ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.976m	3.224ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.877m	3.615ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.805m	3.520ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	30.532m	22.846ms	3	3	100.00
		chip_rv_dm_lc_disabled	7.663m	14.114ms	0	3	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.556h	46.250ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.585h	49.172ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	11.611m	7.661ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.429h	47.508ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	30.532m	22.846ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.526m	1.965ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.519m	2.425ms	3	3	100.00
		rom_volatile_raw_unlock	1.481m	2.467ms	3	3	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	1.182h	17.005ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.260h	19.452ms	3	3	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	12.495m	6.296ms	3	3	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	12.495m	6.296ms	3	3	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	12.495m	6.296ms	3	3	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	6.772m	3.386ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	14.796m	9.821ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	30.794m	19.066ms	3	3	100.00
		chip_sw_otbn_mem_scramble	6.772m	3.386ms	3	3	100.00
		chip_sw_keymgr_key_derivation	34.859m	11.914ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	7.815m	3.665ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.921m	3.171ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	30.794m	19.066ms	3	3	100.00
		chip_sw_otbn_mem_scramble	6.772m	3.386ms	3	3	100.00
		chip_sw_keymgr_key_derivation	34.859m	11.914ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	7.815m	3.665ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.921m	3.171ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	14.796m	9.821ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	7.947m	5.828ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.036m	3.313ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.929m	3.700ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	11.845m	8.003ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	13.604m	6.649ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	12.192m	6.635ms	0	3	0.00
		chip_sw_lc_ctrl_transition	14.796m	9.821ms	15	15	100.00
		chip_prim_tl_access	11.304m	14.838ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	11.304m	14.838ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	22.251m	8.641ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.655m	9.555ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	20.536m	26.119ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	5.947m	7.041ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	9.877m	8.940ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	9.981m	6.918ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	22.266m	25.974ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	17.983m	17.278ms	2	3	66.67
		chip_sw_aon_timer_wdog_bite_reset	11.729m	9.876ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	16.805m	9.780ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	7.618m	5.285ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.655m	9.555ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	7.740m	5.170ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	41.356m	26.009ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	7.499m	6.036ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	7.092m	5.823ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	37.727m	22.520ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	12.290m	7.482ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	20.861m	11.913ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	36.484m	30.987ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.558m	3.358ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	10.087m	6.030ms	95	100	95.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.211m	9.789ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.211m	9.789ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	20.861m	11.913ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	37.727m	22.520ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	7.618m	5.285ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	5.735m	5.585ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.809m	3.411ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	5.958m	3.946ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.246m	5.011ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	22.235m	12.908ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.210m	2.406ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	10.087m	6.030ms	95	100	95.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	24.525m	9.123ms	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	10.659m	4.567ms	3	3	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	11.697m	4.307ms	3	3	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.586m	3.619ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.921m	3.171ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	5.958m	3.946ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	5.958m	3.946ms	0	3	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	18.036m	14.020ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	17.937m	13.475ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.809m	3.411ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.893m	3.991ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	7.205m	6.540ms	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	11.241m	8.154ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	7.663m	14.114ms	0	3	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	12.147m	6.226ms	3	3	100.00
		chip_plic_all_irqs_10	5.986m	4.067ms	3	3	100.00
		chip_plic_all_irqs_20	8.590m	3.866ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.364m	3.091ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.259m	3.043ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.026h	14.681ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.542m	6.296ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.109m	3.300ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	4.108m	3.308ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.832m	2.810ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.815m	3.665ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	6.872m	5.276ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	9.095m	7.421ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	9.416m	7.935ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.714m	7.194ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	10.087m	6.030ms	95	100	95.00
		chip_sw_data_integrity_escalation	9.165m	4.929ms	6	6	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	12.290m	7.482ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	23.123m	24.451ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.756m	3.150ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	5.484m	3.716ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	7.041m	4.473ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	23.123m	24.451ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	23.123m	24.451ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	49.610m	20.090ms	2	3	66.67
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	49.610m	20.090ms	2	3	66.67
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	6.107m	5.943ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	3	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.012m	3.089ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.850m	3.009ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	4.409m	4.314ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.990m	3.546ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	21.505m	7.425ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.872h	31.636ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	39.009m	11.871ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.720m	2.420ms	1	1	100.00
V2		TOTAL			2474	2657	93.11
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	3.835m	3.266ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.469m	2.304ms	1	3	33.33
V2S		TOTAL			4	6	66.67
V3	chip_sw_coremark	chip_sw_coremark	4.335h	72.075ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	21.300m	6.423ms	2	3	66.67
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	2.920m	3.596ms	0	1	0.00
		rom_e2e_jtag_debug_dev	30.608m	11.487ms	1	1	100.00
		rom_e2e_jtag_debug_rma	3.409m	4.385ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	4.867m	4.385ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.484m	3.410ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.874m	5.178ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	22.430s		0	3	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	12.595m	5.781ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	6.019m	2.645ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	24.627m	7.325ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	20.652m	7.629ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	4.653m	2.324ms	3	3	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	12.762m	5.787ms	3	3	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.478m	2.777ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.666m	5.553ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	6.679m	6.434ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	6.640m	4.131ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	20.861m	11.913ms	3	3	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	2.920m	3.596ms	0	1	0.00
		rom_e2e_jtag_debug_dev	30.608m	11.487ms	1	1	100.00
		rom_e2e_jtag_debug_rma	3.409m	4.385ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	8.164m	4.779ms	3	3	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	10.087m	6.030ms	95	100	95.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	4.551m	3.967ms	3	3	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	8.366m	4.455ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.025h	18.253ms	1	1	100.00
V3		TOTAL			42	51	82.35
	Unmapped tests	chip_sival_flash_info_access	3.443m	3.249ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	8.982m	5.317ms	3	3	100.00
		chip_sw_otp_ctrl_rot_auth_config	41.245m	37.634ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.962m	3.225ms	3	3	100.00
		chip_sw_otp_ctrl_descrambling	4.194m	3.378ms	3	3	100.00
		chip_sw_pwrmgr_lowpower_cancel	6.478m	4.136ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	17.679s		0	3	0.00
		chip_sw_flash_ctrl_write_clear	4.647m	2.850ms	3	3	100.00
		TOTAL			2747	2956	92.93

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.60	94.64	92.80	92.19	57.14	93.89	97.25	99.31

Failure Buckets

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 90 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 90 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.48873500005981827628778280256898206609338475200017589094566696963934574625407
    Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3189.492795 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3189.492795 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_alert_handler_lpg_sleep_mode_alerts.74194174186768985743836456316919991921825567007868500069498113466334622480773
    Line 397, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2775.682853 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2775.682853 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 88 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.90494627994490313467367925371319709752891551080132775960862196612813787170078
    Line 613, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.39490524907138197627362927385682715078724728496846614829844141059154931336633
    Line 644, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.15901231101849352817385007602184753537982434758666961180198655582036468312996
    Line 661, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2056742636417677794187104818173228245149074363681015872159364420000903472846
    Line 616, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.385965203256523000013842165266259696838533576793317439234271879765853575448
    Line 656, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
Job timed out after * minutes has 9 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.95943125139346932095541901306194643922072317882853547612879718978733613139315
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job timed out after 120 minutes
```
  - 1.chip_sw_rv_timer_systick_test.71044511349431170190516627616985654398564630132308357618568911260761961123594
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job timed out after 120 minutes
```
  - ... and 1 more failures.
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 3 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.99105562988365660797169578117095573095509536961956289864750009279994287257304
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3868518667799968736803411123841641039935899285512161500522330284484382783719
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 3 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.7396889135288165001275961408427727694352574013098313224234747677609538919913
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
  - 1.chip_sw_alert_handler_lpg_sleep_mode_pings.26976685562620650149253332133685769293098591256430271332693417541457295792427
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
  - ... and 1 more failures.

Job returned non-zero exit code has 6 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 3 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.239178061825708033965070601304455572595360291064614870257066683678634876917
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.209s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_pwrmgr_sleep_wake_5_bug.11687994596306143991167135429500758683252133264490466954612455951640326390512
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.247s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_self_hash has 3 failures.

0.rom_e2e_self_hash.99701352553398108388987596221123458398509154009191665194572258446209603859880
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 7.602s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_self_hash.58816969237200742174430316535620971950024885994537236717233068463021210897505
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 1.609s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.98944760412917393494059627040604999808500860117261803543939883915234605374123
    Line 520, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.114014673695073114490475296219230560187046288981423825329584892873981832119473
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.27811026856059032207915310803086487794822311246870651601238637059417918180869
    Line 494, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.111651050824669123128466760032900040957483951287592263459584606495143136015573
    Line 477, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.110112006435126644888282120716977016225584972392607027313275390161525853294744
    Line 478, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 4 failures:
- Test chip_sw_all_escalation_resets has 4 failures.
  - 22.chip_sw_all_escalation_resets.89654233661991925273471660448435921013562592651391846585272580782763146111769
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3199.896986 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3199.896986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 25.chip_sw_all_escalation_resets.38762967771576282658095269065617647746305994157973918517921695403190310787349
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/25.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3850.779546 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3850.779546 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 3 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 3 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.54981124060708727546660234072200056579420579782447232977867997919512382420376
    Line 587, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 6110.735662 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 6110.735662 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_otp_ctrl_lc_signals_rma.41651140287518238105441812311562721205100667227942366346689302674005310382541
    Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 7052.200950 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 7052.200950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 3 failures:
- Test chip_sw_hmac_oneshot has 3 failures.
  - 0.chip_sw_hmac_oneshot.108351672135184755528904192380515192588478318924359557162001428507209170224924
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2697.695856 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2697.695856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_hmac_oneshot.87436588091858266257013451407448345797757543692894284471691263936143787164689
    Line 393, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2442.329219 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2442.329219 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 3 failures:

Test chip_rv_dm_lc_disabled has 3 failures.

0.chip_rv_dm_lc_disabled.62872791534556573146973957789307964114942901566918382268083917747654409651840
Line 209, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log

  UVM_ERROR @ 4271.081658 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x105fc read out mismatch
  UVM_INFO @ 4271.081658 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_rv_dm_lc_disabled.83198331269979083497546250265711496395655339158889968823895500966696402540047
Line 219, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log

  UVM_ERROR @ 4531.878393 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10424 read out mismatch
  UVM_INFO @ 4531.878393 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 3 failures:

Test chip_sw_power_idle_load has 3 failures.

0.chip_sw_power_idle_load.1526011683794917562891977893871336161799010168341843071159559998674125171541
Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log

  UVM_ERROR @ 3331.519000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3331.519000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_power_idle_load.22132482648532100434482404749040178611111093294454481663147852407404468309840
Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_idle_load/latest/run.log

  UVM_ERROR @ 3300.710000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3300.710000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 3 failures:
- Test chip_sw_power_sleep_load has 3 failures.
  - 0.chip_sw_power_sleep_load.113149437704811174561843164226783766326051383945907434988970406994565260853817
    Line 403, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3314.854500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3314.854500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.chip_sw_power_sleep_load.19692485602319301658095329577586861777138260784079689896454800801299100346961
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3352.652000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3352.652000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.109619150853601683920825746635422495616363002235794291987901862636723689689493
    Line 685, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.108244884034407461352407362028404404053684555371730205666500516210005365357114
    Line 677, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.30669295351418345233621796121742371159844920133422769068067807055194593939092
    Line 659, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 2 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 2 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.104208642861197031244651475450329466208896770732767947501673892528628684405496
    Line 764, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3577.472000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3577.472000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.chip_sw_sleep_pin_mio_dio_val.68625402436651537164004353513627074842166125143236502638270755139375723051145
    Line 533, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3245.644000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3245.644000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch has 2 failures:

Test chip_sw_spi_device_pass_through_collision has 2 failures.

0.chip_sw_spi_device_pass_through_collision.44932690817567261508417920973035827455797993365126155659416956725518352482324
Line 625, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log

  UVM_ERROR @ 3363.946409 us: (chip_sw_spi_passthrough_collision_vseq.sv:183) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] Compare mismatch
  host_rsp:
  -------------------------------------------------------------------------
  Name                               Type              Size  Value
  -------------------------------------------------------------------------

1.chip_sw_spi_device_pass_through_collision.102225597443899458175132116945138611489480668493706178601668359950629177915971
Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log

  UVM_ERROR @ 3299.895451 us: (chip_sw_spi_passthrough_collision_vseq.sv:183) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] Compare mismatch
  host_rsp:
  -------------------------------------------------------------------------
  Name                               Type              Size  Value
  -------------------------------------------------------------------------

UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 2 failures:

Test chip_sw_rv_core_ibex_lockstep_glitch has 2 failures.

0.chip_sw_rv_core_ibex_lockstep_glitch.51937218380439699250555207427977231355214096593117232521914012189568361958188
Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log

  UVM_FATAL @ 2953.236430 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2953.236430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_rv_core_ibex_lockstep_glitch.95454259085758442594861649203452674770983305268353082903464369643436830897713
Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log

  UVM_FATAL @ 2652.007513 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 2652.007513 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.77441865557250727057616472398796003025823794696734346863329284975492964954117
    Line 663, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.61324177406820717647735393917135555260860541066942873550780986365825519609260
    Line 533, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.62273571586179350517023295402205242427230876277552279468477174538502509809968
    Line 754, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.40324164769983070463152681383114483691394849688871746558460453987426378994548
    Line 557, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 2 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.108535061113249758420411416729042239669327357459878445176131512104814965501687
    Line 502, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 3596.054752 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 3596.054752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.20359847979789170086071018669376035676397938348492390569383241603770652276590
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_ERROR @ 4384.604180 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 4384.604180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 2 failures:
- Test chip_sw_alert_test has 2 failures.
  - 1.chip_sw_alert_test.25437719434574107300102690095613161983898391023649120899859161777651181604692
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3368.637332 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 3368.637332 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.chip_sw_alert_test.108290130914064803809700677997836515188565980262969706958389058216277955419656
    Line 389, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3135.184656 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 3135.184656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31796) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_tl_errors has 1 failures.

16.chip_tl_errors.90493107438037323260722872620534030086453716916620174752843499882514540705053
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2664.543904 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31796) { a_addr: 'h1047c  a_data: 'h67b9799d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8  a_opcode: 'h4  a_user: 'h19913  d_param: 'h0  d_source: 'h8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2664.543904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

19.chip_csr_mem_rw_with_rand_reset.63635179717331372452695688675732085819173572490730536721322297045932929334690
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2721.118798 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31796) { a_addr: 'h10300  a_data: 'h1b0d810  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h4  a_user: 'h18ad5  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2721.118798 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.42341979990400580710539356763238899726951714421435552335463174148031630054683
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 37633.918854 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 37633.918854 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@113714) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.7315426698433146356201227647481011411214290538375746748847914093383976775540
Line 429, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4490.841208 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@113714) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4490.841208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:

Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.

0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2870196789263121632816930339944697005548792896720512488789627834656382795855
Line 465, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log

      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_pwrmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 10106633988ps failed at 10106633988ps
      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_pwrmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 10106717316ps failed at 10106717316ps
      Offending '(pend_req[h2d.a_source].pend == 0)'

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.106629647324566870420412448642388578176339478671266850081279595997285888089525
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3512.554360 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3512.554360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34724) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.87621170711090800938798707535416546423355142395984882903608274752999170324818
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2461.368750 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34724) { a_addr: 'h10778  a_data: 'h9add589f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h11  a_opcode: 'h4  a_user: 'h199a2  d_param: 'h0  d_source: 'h11  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2461.368750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.66439564410171743143035795365458031931246841664826597519752200091117264636637
    Line 588, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.115325622531011572314605157482375958893678730280756988899658460686218278280143
    Line 623, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32438) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.45831644342283188596502659870274594843961774921858087388421111991323770295425
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1853.528190 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32438) { a_addr: 'h104c8  a_data: 'h39d27651  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h19958  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1853.528190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@109370) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

1.chip_sw_rstmgr_cpu_info.101392067253452643698855795970903031620062848927477723372064520549820072389231
Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3945.573336 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@109370) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3945.573336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 1.chip_sw_sysrst_ctrl_ec_rst_l.176113041741332797835492905207114067221292723700324185107823864045957088148
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 10953.223795 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 10953.223795 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31992) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

1.chip_tl_errors.94351341928655776720352830562464109801828003408435249104384157622540607914743
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2093.240068 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31992) { a_addr: 'h104d0  a_data: 'h6fc0f4a1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8  a_opcode: 'h4  a_user: 'h1a92f  d_param: 'h0  d_source: 'h8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2093.240068 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 1.chip_sw_ast_clk_rst_inputs.97154107989542853702527222960337170442752492746170179291070261372775644253928
    Line 435, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 23335.452458 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 23335.452458 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 2.chip_sw_spi_device_pass_through_collision.33790883362492711501072059095495804377716941015968795620590880791035397507885
    Line 405, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3088.432205 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3088.432205 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@88466) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

2.chip_sw_rstmgr_cpu_info.93522380448439117516546348137567807650778864116907033910594068506455607454292
Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3282.547304 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@88466) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3282.547304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33602) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

2.chip_tl_errors.82645108212339567104020654527514495587834537242017161130512871797472193384659
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2447.187685 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33602) { a_addr: 'h10110  a_data: 'haee18aa2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h25  a_opcode: 'h4  a_user: 'h1a56c  d_param: 'h0  d_source: 'h25  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2447.187685 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 2.chip_sw_power_virus.104922681950816800713859355686207493605358749581977149855648311212623499653967
    Line 440, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3836.144571 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3836.144571 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement has 1 failures:
- Test rom_raw_unlock has 1 failures.
  - 2.rom_raw_unlock.54640177103322522918733678479832286204093932454461361450568772506155197660939
    Line 423, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.rom_raw_unlock/latest/run.log
```
  UVM_FATAL @ 15200.065700 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
  UVM_INFO @ 15200.065700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32034) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

2.chip_csr_mem_rw_with_rand_reset.32627088194933232317695851192127604904057045210987192286637392473849304875479
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2727.361013 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32034) { a_addr: 'h104a8  a_data: 'h9072e1f3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h25  a_opcode: 'h4  a_user: 'h1a93e  d_param: 'h0  d_source: 'h25  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2727.361013 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32864) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

3.chip_tl_errors.94109224419085100904475911776232994194581610157223396515803331079977108418590
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/3.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2438.431048 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32864) { a_addr: 'h10760  a_data: 'h11564fc1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h1a9fa  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2438.431048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33918) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

4.chip_tl_errors.13768616507797287158634104601018477389798246943853598433434497016886613743682
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2376.519400 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33918) { a_addr: 'h1073c  a_data: 'h9bb9844f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3f  a_opcode: 'h4  a_user: 'h1bdd3  d_param: 'h0  d_source: 'h3f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2376.519400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33460) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

5.chip_tl_errors.64922648489082136060097650414431344969794239288657678460799420816622531990361
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2208.253030 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33460) { a_addr: 'h106f8  a_data: 'h14be7e35  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h1ae32  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2208.253030 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37002) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

7.chip_tl_errors.56184830487059910098382557412808287787178828960086910729753560988112444768941
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2020.207230 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37002) { a_addr: 'h105b0  a_data: 'hb0494463  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1d  a_opcode: 'h4  a_user: 'h19e02  d_param: 'h0  d_source: 'h1d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2020.207230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36462) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

7.chip_csr_mem_rw_with_rand_reset.114916080053987775290848958660926048796909232052973041839896808429485192178825
Line 223, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2584.567904 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36462) { a_addr: 'hbb8  a_data: 'h186132f4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h0  a_user: 'h27a30  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2584.567904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37584) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

8.chip_tl_errors.29983321388988194432608628337914532494456062167375569754957426021158545600626
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2368.649730 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37584) { a_addr: 'h10730  a_data: 'hce1e40b7  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h17  a_opcode: 'h4  a_user: 'h1a5f5  d_param: 'h0  d_source: 'h17  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2368.649730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38240) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

9.chip_tl_errors.43626787038189004006764902932377418943431339814991130107242219697606000179073
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2362.060784 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38240) { a_addr: 'h1060c  a_data: 'h8a7cc47  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h4  a_user: 'h186eb  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2362.060784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32146) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

9.chip_csr_mem_rw_with_rand_reset.70672120635931357251954494999915305251422339068592230588809998303286502624162
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2069.151580 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32146) { a_addr: 'h10758  a_data: 'hdf968f34  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h4  a_user: 'h18150  d_param: 'h0  d_source: 'h13  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2069.151580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31974) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

10.chip_tl_errors.91493479201320985075652149409055440328996050770309457145245867639163276211932
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1706.235116 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31974) { a_addr: 'h10404  a_data: 'h5cca857d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h4  a_user: 'h1993a  d_param: 'h0  d_source: 'h1e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1706.235116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32182) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

10.chip_csr_mem_rw_with_rand_reset.20033174291486061478381090490946698553188596683787083561002418706780832204028
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2846.081496 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32182) { a_addr: 'h10530  a_data: 'h494ef1e3  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h4  a_user: 'h1aefe  d_param: 'h0  d_source: 'h1e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2846.081496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31932) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

11.chip_tl_errors.98650715008691248160086100181013353489539026241338089109363082117487410112361
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3029.967472 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31932) { a_addr: 'h10424  a_data: 'hb2fc03b2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h4  a_user: 'h181eb  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3029.967472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32128) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

12.chip_tl_errors.83733746681033633087377523934271059547436528922457547907182107814489670466357
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2656.701064 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32128) { a_addr: 'h10798  a_data: 'h5097d288  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h25  a_opcode: 'h4  a_user: 'h1994e  d_param: 'h0  d_source: 'h25  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2656.701064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@215638) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

12.chip_csr_mem_rw_with_rand_reset.91969533292385793968379407231579087527070325584295101827872058126830401478540
Line 239, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 6027.508243 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@215638) { a_addr: 'h10570  a_data: 'h3f3785ef  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h4  a_user: 'h1862d  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 6027.508243 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@132464) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

13.chip_tl_errors.60981627745845741120654786980487721643587201753052687185411513314846729454338
Line 215, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2953.108341 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@132464) { a_addr: 'h10638  a_data: 'h4951be99  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h33  a_opcode: 'h4  a_user: 'h1b638  d_param: 'h0  d_source: 'h33  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2953.108341 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32394) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

14.chip_tl_errors.43738570170376859303154750514692957810932229426296699611690375020630302218717
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2661.752734 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32394) { a_addr: 'h107d8  a_data: 'ha1665f94  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1d  a_opcode: 'h4  a_user: 'h1b19a  d_param: 'h0  d_source: 'h1d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2661.752734 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33000) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

14.chip_csr_mem_rw_with_rand_reset.59096102753706841994214726598015474003485205224957980972505484467315208300819
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2445.734999 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33000) { a_addr: 'h104d8  a_data: 'hcbdf6216  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h4  a_user: 'h1bded  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2445.734999 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31890) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

15.chip_tl_errors.109406711463808980445697340719849354608662786235220520474721682653754953864800
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2276.601910 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31890) { a_addr: 'h105c4  a_data: 'h2641774f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h9  a_opcode: 'h4  a_user: 'h18651  d_param: 'h0  d_source: 'h9  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2276.601910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31930) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

15.chip_csr_mem_rw_with_rand_reset.29872275798157568230931186521002553874757368440861430438940944818156798330830
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2843.412040 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31930) { a_addr: 'h10384  a_data: 'h8dd2daae  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h4  a_opcode: 'h4  a_user: 'h1b6c9  d_param: 'h0  d_source: 'h4  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2843.412040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32784) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

16.chip_csr_mem_rw_with_rand_reset.24635875426539303283873697575460046909439077529403325976891672674235222242324
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2345.262937 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32784) { a_addr: 'h1067c  a_data: 'h699a5726  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h4  a_user: 'h1922f  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2345.262937 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32772) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

17.chip_tl_errors.17670811391161392383475522969173857944146883428904048894451456600946368501901
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2054.267283 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32772) { a_addr: 'h10710  a_data: 'h6ec44b94  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h38  a_opcode: 'h4  a_user: 'h1bd0f  d_param: 'h0  d_source: 'h38  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2054.267283 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32180) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

17.chip_csr_mem_rw_with_rand_reset.82527035343201143141015305641325743030651600994368079393733575899912211211567
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2527.623110 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32180) { a_addr: 'h107d0  a_data: 'h54fe1bf5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1f  a_opcode: 'h4  a_user: 'h1a567  d_param: 'h0  d_source: 'h1f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2527.623110 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32744) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

18.chip_tl_errors.37587865329641799935022428945764178841518486681899474028258959406200583065320
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2896.860234 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32744) { a_addr: 'h1033c  a_data: 'hf31685a9  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h20  a_opcode: 'h4  a_user: 'h1aea5  d_param: 'h0  d_source: 'h20  d_data: 'h517  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd10  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2896.860234 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34808) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

19.chip_tl_errors.49474844303779838310931236787302989891078505168672758678322912807057672102216
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1731.149888 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34808) { a_addr: 'h1056c  a_data: 'h461e8380  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h1baf4  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1731.149888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32776) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

20.chip_tl_errors.22320665674316416968751112573534390228375715897728277518776695714785515768096
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/20.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2791.317640 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32776) { a_addr: 'h10428  a_data: 'h64d00a5b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h25  a_opcode: 'h4  a_user: 'h199ce  d_param: 'h0  d_source: 'h25  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2791.317640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32036) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

22.chip_tl_errors.54657538594842284183658107809342166018901524449953256063983798167504544282139
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2230.536800 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32036) { a_addr: 'h10790  a_data: 'hb311bc31  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h4  a_user: 'h18dcb  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2230.536800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32300) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

24.chip_tl_errors.86370052915940951244915992742858223345663649786544319876303670023019834896018
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/24.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2361.588647 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32300) { a_addr: 'h10658  a_data: 'h3e29caa5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h18654  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2361.588647 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33268) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

25.chip_tl_errors.7142519389644773350868418611375088672610782788195370910857226827047731841734
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/25.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2139.969492 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33268) { a_addr: 'h1048c  a_data: 'h3c3e275c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1b  a_opcode: 'h4  a_user: 'h1bd28  d_param: 'h0  d_source: 'h1b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2139.969492 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32976) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

26.chip_tl_errors.94912101215229837995765496850274489224933875753666364488627884064266921384943
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2037.077802 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32976) { a_addr: 'h10710  a_data: 'hfef846b8  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h7  a_opcode: 'h4  a_user: 'h1bd1d  d_param: 'h0  d_source: 'h7  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2037.077802 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41360) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

27.chip_tl_errors.83787305280270551009113517694524818902473599774271806123118580020774818642610
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1787.893000 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41360) { a_addr: 'h106c0  a_data: 'hef81d81b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1d  a_opcode: 'h4  a_user: 'h186c7  d_param: 'h0  d_source: 'h1d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1787.893000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31944) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

28.chip_tl_errors.47862731567819440080883208671863622122812919197181011026249587835958606402240
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2649.189570 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31944) { a_addr: 'h10538  a_data: 'h26a55738  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h4  a_user: 'h1ba00  d_param: 'h0  d_source: 'h2b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2649.189570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@181836) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

29.chip_tl_errors.38607219744642555334991057927163381239200647647894993284129215070675021318408
Line 215, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/29.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2851.549290 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@181836) { a_addr: 'h107d0  a_data: 'h79142cb0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2e  a_opcode: 'h4  a_user: 'h1a544  d_param: 'h0  d_source: 'h2e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2851.549290 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:905) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 89.chip_sw_all_escalation_resets.5549712828606095641791813248890250209532787015628628727084827672789668912661
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/89.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2475.335190 us: (cip_base_vseq.sv:905) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
  UVM_INFO @ 2475.335190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```