ADC_CTRL Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: `06d697f`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	21.310s	6.107ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.800s	1.230ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.840s	562.847us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.912m	52.637ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.760s	1.058ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.130s	562.476us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.840s	562.847us	20	20	100.00
		adc_ctrl_csr_aliasing	5.760s	1.058ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.483m	489.999ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	18.224m	503.123ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	21.465m	487.970ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.006m	494.563ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	23.081m	615.407ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	23.784m	602.459ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.776m	600.000ms	47	50	94.00
V2	clock_gating	adc_ctrl_clock_gating	22.302m	2.000s	36	50	72.00
V2	poweron_counter	adc_ctrl_poweron_counter	16.180s	4.707ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.002m	40.939ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	5.785m	117.033ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	35.649m	1.134s	48	50	96.00
V2	alert_test	adc_ctrl_alert_test	2.410s	466.359us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	2.510s	501.551us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.160s	489.797us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.160s	489.797us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.800s	1.230ms	5	5	100.00
		adc_ctrl_csr_rw	2.840s	562.847us	20	20	100.00
		adc_ctrl_csr_aliasing	5.760s	1.058ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.060s	4.838ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.800s	1.230ms	5	5	100.00
		adc_ctrl_csr_rw	2.840s	562.847us	20	20	100.00
		adc_ctrl_csr_aliasing	5.760s	1.058ms	5	5	100.00
		adc_ctrl_same_csr_outstanding	18.060s	4.838ms	20	20	100.00
V2		TOTAL			721	740	97.43
V2S	tl_intg_err	adc_ctrl_sec_cm	24.460s	8.012ms	5	5	100.00
		adc_ctrl_tl_intg_err	27.730s	7.963ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	27.730s	7.963ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	22.224m	10.000s	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			896	920	97.39

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.37	99.05	96.03	100.00	100.00	98.64	95.95	91.96

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 18 failures:
- Test adc_ctrl_clock_gating has 11 failures.
  - 0.adc_ctrl_clock_gating.38303733456595162470114009067449391051104454101479033691775320309615728810451
    Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 20.adc_ctrl_clock_gating.5791727876785016359346874279153506898476015851774019528180424427443336549006
    Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/20.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
- Test adc_ctrl_filters_both has 2 failures.
  - 8.adc_ctrl_filters_both.105146659922361283793974975251016641754383941833950452003213148756988861928431
    Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/8.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 18.adc_ctrl_filters_both.27066210409466010928455813995187396119468592002240816916621097000690023132743
    Line 180, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/18.adc_ctrl_filters_both/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_stress_all_with_rand_reset has 4 failures.
  - 9.adc_ctrl_stress_all_with_rand_reset.90084531320500235861710360006189502896421802963392026227111473027353810046660
    Line 154, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 15.adc_ctrl_stress_all_with_rand_reset.52385403251775394529580068878191631586002718166891005446076168747409967178324
    Line 195, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/15.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
- Test adc_ctrl_stress_all has 1 failures.
  - 24.adc_ctrl_stress_all.81176713641252982206482379136142424846329624430818901721582919830045265740114
    Line 253, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/24.adc_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 4 failures:

Test adc_ctrl_stress_all has 1 failures.

7.adc_ctrl_stress_all.52480257182897146009734298068135131649400855030933563537605237551834642822971
Line 169, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/7.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 280116477567 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 280116477567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_clock_gating has 2 failures.

17.adc_ctrl_clock_gating.108635468414127438845230365906121559820035243595616115744129606746464770383605
Line 182, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/17.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 354806344959 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 354806344959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.adc_ctrl_clock_gating.23266063300838868136056349518285907771108340429223062360120640439334751322680
Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/18.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 172632562961 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 172632562961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
- 31.adc_ctrl_stress_all_with_rand_reset.68710531838984311721758151777687206514160289396486171105602458005337593898257
  Line 161, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/31.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2029553253 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 2029553253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 2 failures:
- Test adc_ctrl_filters_both has 1 failures.
  - 6.adc_ctrl_filters_both.31934148596950875106956348705201853697424066739085230333154951529004928488155
    Line 164, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/6.adc_ctrl_filters_both/latest/run.log
```
  UVM_ERROR @ 340393438025 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 340393438025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_clock_gating has 1 failures.
  - 11.adc_ctrl_clock_gating.107281336849099785560600599829460887350789829956538418360567726603340690439425
    Line 148, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 99358824608 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 99358824608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```