AES/MASKED Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: `06d697f`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	30.000s	59.746us	1	1	100.00
V1	smoke	aes_smoke	31.000s	147.678us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	116.754us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	77.815us	19	20	95.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	781.230us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	569.790us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	99.341us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	77.815us	19	20	95.00
		aes_csr_aliasing	4.000s	569.790us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	31.000s	147.678us	50	50	100.00
		aes_config_error	47.000s	3.704ms	50	50	100.00
		aes_stress	34.000s	1.603ms	50	50	100.00
V2	key_length	aes_smoke	31.000s	147.678us	50	50	100.00
		aes_config_error	47.000s	3.704ms	50	50	100.00
		aes_stress	34.000s	1.603ms	50	50	100.00
V2	back2back	aes_stress	34.000s	1.603ms	50	50	100.00
		aes_b2b	50.000s	498.045us	50	50	100.00
V2	backpressure	aes_stress	34.000s	1.603ms	50	50	100.00
V2	multi_message	aes_smoke	31.000s	147.678us	50	50	100.00
		aes_config_error	47.000s	3.704ms	50	50	100.00
		aes_stress	34.000s	1.603ms	50	50	100.00
		aes_alert_reset	32.000s	193.146us	50	50	100.00
V2	failure_test	aes_man_cfg_err	30.000s	144.586us	50	50	100.00
		aes_config_error	47.000s	3.704ms	50	50	100.00
		aes_alert_reset	32.000s	193.146us	50	50	100.00
V2	trigger_clear_test	aes_clear	31.000s	100.649us	49	50	98.00
V2	nist_test_vectors	aes_nist_vectors	38.000s	2.129ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	32.000s	193.146us	50	50	100.00
V2	stress	aes_stress	34.000s	1.603ms	50	50	100.00
V2	sideload	aes_stress	34.000s	1.603ms	50	50	100.00
		aes_sideload	33.000s	283.468us	50	50	100.00
V2	deinitialization	aes_deinit	34.000s	197.898us	50	50	100.00
V2	stress_all	aes_stress_all	1.033m	6.064ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	69.881us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	177.610us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	177.610us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	116.754us	5	5	100.00
		aes_csr_rw	3.000s	77.815us	19	20	95.00
		aes_csr_aliasing	4.000s	569.790us	5	5	100.00
		aes_same_csr_outstanding	3.000s	139.858us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	116.754us	5	5	100.00
		aes_csr_rw	3.000s	77.815us	19	20	95.00
		aes_csr_aliasing	4.000s	569.790us	5	5	100.00
		aes_same_csr_outstanding	3.000s	139.858us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	47.000s	756.112us	50	50	100.00
V2S	fault_inject	aes_fi	30.000s	85.932us	50	50	100.00
		aes_control_fi	59.000s	10.005ms	281	300	93.67
		aes_cipher_fi	59.000s	10.004ms	346	350	98.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	308.637us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	308.637us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	308.637us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	308.637us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	220.482us	19	20	95.00
V2S	tl_intg_err	aes_sec_cm	7.000s	1.134ms	5	5	100.00
		aes_tl_intg_err	6.000s	3.603ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	3.603ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	32.000s	193.146us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	308.637us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	31.000s	147.678us	50	50	100.00
		aes_stress	34.000s	1.603ms	50	50	100.00
		aes_alert_reset	32.000s	193.146us	50	50	100.00
		aes_core_fi	1.050m	10.051ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	308.637us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	32.000s	185.238us	50	50	100.00
		aes_stress	34.000s	1.603ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	34.000s	1.603ms	50	50	100.00
		aes_sideload	33.000s	283.468us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	32.000s	185.238us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	32.000s	185.238us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	32.000s	185.238us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	32.000s	185.238us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	32.000s	185.238us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	34.000s	1.603ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	34.000s	1.603ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	30.000s	85.932us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	30.000s	85.932us	50	50	100.00
		aes_control_fi	59.000s	10.005ms	281	300	93.67
		aes_cipher_fi	59.000s	10.004ms	346	350	98.86
		aes_ctr_fi	17.000s	49.149us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	30.000s	85.932us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	30.000s	85.932us	50	50	100.00
		aes_control_fi	59.000s	10.005ms	281	300	93.67
		aes_cipher_fi	59.000s	10.004ms	346	350	98.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	59.000s	10.004ms	346	350	98.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	30.000s	85.932us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	30.000s	85.932us	50	50	100.00
		aes_control_fi	59.000s	10.005ms	281	300	93.67
		aes_ctr_fi	17.000s	49.149us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	30.000s	85.932us	50	50	100.00
		aes_control_fi	59.000s	10.005ms	281	300	93.67
		aes_cipher_fi	59.000s	10.004ms	346	350	98.86
		aes_ctr_fi	17.000s	49.149us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	32.000s	193.146us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	30.000s	85.932us	50	50	100.00
		aes_control_fi	59.000s	10.005ms	281	300	93.67
		aes_cipher_fi	59.000s	10.004ms	346	350	98.86
		aes_ctr_fi	17.000s	49.149us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	30.000s	85.932us	50	50	100.00
		aes_control_fi	59.000s	10.005ms	281	300	93.67
		aes_cipher_fi	59.000s	10.004ms	346	350	98.86
		aes_ctr_fi	17.000s	49.149us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	30.000s	85.932us	50	50	100.00
		aes_control_fi	59.000s	10.005ms	281	300	93.67
		aes_ctr_fi	17.000s	49.149us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	30.000s	85.932us	50	50	100.00
		aes_control_fi	59.000s	10.005ms	281	300	93.67
		aes_cipher_fi	59.000s	10.004ms	346	350	98.86
V2S		TOTAL			959	985	97.36
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	44.000s	634.722us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1564	1602	97.63

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.36	98.62	96.50	99.43	95.43	97.99	97.78	98.36	98.59

Failure Buckets

Job timed out after * minutes has 12 failures:
- Test aes_control_fi has 11 failures.
  - 35.aes_control_fi.57132407006480586960058855539327686452001183327590270809525587418305626237678
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 98.aes_control_fi.106784907632008551064028958322592643442918411578998989977731468802407079887583
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/98.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 9 more failures.
- Test aes_cipher_fi has 1 failures.
  - 267.aes_cipher_fi.25953432604872139041500021638264981729110169901026784720507870373652704871902
    Log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/267.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 50.aes_control_fi.43460044727141671785536797645021586241188319242546937116987336436838948422859
    Line 133, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/50.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011524767 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011524767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 168.aes_control_fi.46069021503322169675722765788228362417169090497077380883811876241272722692441
    Line 142, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/168.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10016226541 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016226541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.77201056832578530301705906391289618612982342480305847643083594349320273245815
Line 480, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2052163515 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2052163515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.97227373312629163600658028137368965802317418771143879061638809858363798509002
Line 553, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1033150730 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1033150730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 0.aes_stress_all_with_rand_reset.6508460906938768746443488841568744761739713875966549709112594814135807779699
    Line 483, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 567566234 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 567566234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.aes_stress_all_with_rand_reset.84256836135252174185000651899320903814898993120214824594832768114581239947312
    Line 195, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1282822290 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1282822290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_cipher_fi has 3 failures.
  - 134.aes_cipher_fi.34958847459053717970996354637376158567744216474707596311221647857471315884557
    Line 141, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/134.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009397355 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009397355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 172.aes_cipher_fi.35971365862551797690697969105120481954376763345505891943175098324137346470324
    Line 144, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/172.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004055916 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004055916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,876): Assertion AesSecCmKeyMaskingStateShare has failed (* cycles, starting * PS) has 2 failures:

Test aes_shadow_reg_errors_with_csr_rw has 1 failures.

5.aes_shadow_reg_errors_with_csr_rw.115322268395609481335138540859778089397804163911961824331263077363728012428847
Line 106, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/5.aes_shadow_reg_errors_with_csr_rw/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,876): (time 137040926 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.gen_sec_cm_key_masking_share_svas[1].AesSecCmKeyMaskingStateShare has failed (2 cycles, starting 136999259 PS)
  UVM_ERROR @ 137040926 ps: (aes_cipher_core.sv:876) [ASSERT FAILED] AesSecCmKeyMaskingStateShare
  UVM_INFO @ 137040926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_csr_rw has 1 failures.

12.aes_csr_rw.3505204532831960300118425163173619298558314405033173921065143048503643389133
Line 106, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/12.aes_csr_rw/latest/run.log

  xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/cover_reg_top/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,876): (time 33291619 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.gen_sec_cm_key_masking_share_svas[1].AesSecCmKeyMaskingStateShare has failed (2 cycles, starting 33251619 PS)
  UVM_ERROR @  33291619 ps: (aes_cipher_core.sv:876) [ASSERT FAILED] AesSecCmKeyMaskingStateShare
  UVM_INFO @  33291619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.79205463446419885767805675455936168476920853730824074072496057013278689038021
    Line 317, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1302335618 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1302335618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.24310971664764436730249676782324946103929130574882507312360569215311396265223
    Line 1145, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2407845465 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2407845465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 21.aes_core_fi.79085373676589378202163546191020202370681406226033928981208073622066210888970
    Line 131, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/21.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10051126277 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x8c1e8c84, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10051126277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:611) scoreboard [scoreboard] # * has 1 failures:
- Test aes_clear has 1 failures.
  - 39.aes_clear.52269987124141224067911578666482467009837809476863220311893373096348862288276
    Line 9353, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/39.aes_clear/latest/run.log
```
  UVM_FATAL @ 222044148 ps: (aes_scoreboard.sv:611) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]  # 0
           TEST FAILED MESSAGES DID NOT MATCH

                 0 1d 	 9d 	 5f 	 0
                 1 00 	 5a 	 0c 	 0
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_control_fi has 1 failures.
  - 56.aes_control_fi.86749717241869222328868675260894121458846256576390194786547082086381499248320
    Line 138, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/56.aes_control_fi/latest/run.log
```
  UVM_ERROR @  23873042 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  23873042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 63.aes_core_fi.54378336707475294650100046935976712248410610040724789203012459995776675530792
    Line 139, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/63.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10018622606 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018622606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```