AES/UNMASKED Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: `06d697f`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	75.664us	1	1	100.00
V1	smoke	aes_smoke	4.000s	183.170us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	119.151us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	66.530us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	2.072ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	3.000s	1.069ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	68.382us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	66.530us	20	20	100.00
		aes_csr_aliasing	3.000s	1.069ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	183.170us	50	50	100.00
		aes_config_error	3.000s	283.713us	50	50	100.00
		aes_stress	4.000s	702.951us	50	50	100.00
V2	key_length	aes_smoke	4.000s	183.170us	50	50	100.00
		aes_config_error	3.000s	283.713us	50	50	100.00
		aes_stress	4.000s	702.951us	50	50	100.00
V2	back2back	aes_stress	4.000s	702.951us	50	50	100.00
		aes_b2b	8.000s	480.878us	50	50	100.00
V2	backpressure	aes_stress	4.000s	702.951us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	183.170us	50	50	100.00
		aes_config_error	3.000s	283.713us	50	50	100.00
		aes_stress	4.000s	702.951us	50	50	100.00
		aes_alert_reset	4.000s	1.148ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	134.313us	50	50	100.00
		aes_config_error	3.000s	283.713us	50	50	100.00
		aes_alert_reset	4.000s	1.148ms	50	50	100.00
V2	trigger_clear_test	aes_clear	4.000s	106.209us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	4.000s	210.455us	1	1	100.00
V2	reset_recovery	aes_alert_reset	4.000s	1.148ms	50	50	100.00
V2	stress	aes_stress	4.000s	702.951us	50	50	100.00
V2	sideload	aes_stress	4.000s	702.951us	50	50	100.00
		aes_sideload	6.000s	343.011us	50	50	100.00
V2	deinitialization	aes_deinit	4.000s	90.599us	50	50	100.00
V2	stress_all	aes_stress_all	15.000s	418.924us	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	58.152us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	4.000s	97.402us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	4.000s	97.402us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	119.151us	5	5	100.00
		aes_csr_rw	3.000s	66.530us	20	20	100.00
		aes_csr_aliasing	3.000s	1.069ms	5	5	100.00
		aes_same_csr_outstanding	3.000s	69.805us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	119.151us	5	5	100.00
		aes_csr_rw	3.000s	66.530us	20	20	100.00
		aes_csr_aliasing	3.000s	1.069ms	5	5	100.00
		aes_same_csr_outstanding	3.000s	69.805us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	4.000s	130.976us	50	50	100.00
V2S	fault_inject	aes_fi	4.000s	84.669us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	280	300	93.33
		aes_cipher_fi	28.000s	10.005ms	328	350	93.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	114.843us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	114.843us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	114.843us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	114.843us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	672.858us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	554.647us	5	5	100.00
		aes_tl_intg_err	3.000s	182.343us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	3.000s	182.343us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	4.000s	1.148ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	114.843us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	183.170us	50	50	100.00
		aes_stress	4.000s	702.951us	50	50	100.00
		aes_alert_reset	4.000s	1.148ms	50	50	100.00
		aes_core_fi	2.133m	10.026ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	114.843us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	70.425us	50	50	100.00
		aes_stress	4.000s	702.951us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	4.000s	702.951us	50	50	100.00
		aes_sideload	6.000s	343.011us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	70.425us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	70.425us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	70.425us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	70.425us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	70.425us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	4.000s	702.951us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	4.000s	702.951us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	4.000s	84.669us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	4.000s	84.669us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	280	300	93.33
		aes_cipher_fi	28.000s	10.005ms	328	350	93.71
		aes_ctr_fi	3.000s	107.003us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	4.000s	84.669us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	4.000s	84.669us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	280	300	93.33
		aes_cipher_fi	28.000s	10.005ms	328	350	93.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	28.000s	10.005ms	328	350	93.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	4.000s	84.669us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	4.000s	84.669us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	280	300	93.33
		aes_ctr_fi	3.000s	107.003us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	4.000s	84.669us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	280	300	93.33
		aes_cipher_fi	28.000s	10.005ms	328	350	93.71
		aes_ctr_fi	3.000s	107.003us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	4.000s	1.148ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	4.000s	84.669us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	280	300	93.33
		aes_cipher_fi	28.000s	10.005ms	328	350	93.71
		aes_ctr_fi	3.000s	107.003us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	4.000s	84.669us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	280	300	93.33
		aes_cipher_fi	28.000s	10.005ms	328	350	93.71
		aes_ctr_fi	3.000s	107.003us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	4.000s	84.669us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	280	300	93.33
		aes_ctr_fi	3.000s	107.003us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	4.000s	84.669us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	280	300	93.33
		aes_cipher_fi	28.000s	10.005ms	328	350	93.71
V2S		TOTAL			939	985	95.33
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	34.000s	2.021ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1546	1602	96.50

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.14	97.60	94.58	98.76	92.94	98.07	91.85	98.08	97.18

Failure Buckets

Job timed out after * minutes has 27 failures:
- Test aes_control_fi has 13 failures.
  - 19.aes_control_fi.64644215328294577182307162386786763955089694969993517026171784325855985602787
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 58.aes_control_fi.35464573015568901800512196026142142973311444485501153493389237487094752529038
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/58.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 11 more failures.
- Test aes_cipher_fi has 14 failures.
  - 25.aes_cipher_fi.41893285005419033778576810866385134927188953632003937069862940003079722251835
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 26.aes_cipher_fi.114780225032169817580971724075024937718173354477502472513205866696982948981576
    Log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/26.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 113.aes_cipher_fi.108724701774436514673461593612013285850280257930811168729825413522085318083643
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/113.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004705346 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004705346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 212.aes_cipher_fi.106559014826924949044328653418828632900784525121678058076997704088192743674478
    Line 139, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/212.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004671656 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004671656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

2.aes_stress_all_with_rand_reset.60088380187986524086478985675950833571514819962996091617193579610163089290422
Line 1539, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4528421744 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4528421744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.61867019155058498577624585783200343256126784577766971564778917452314508413502
Line 330, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 347574910 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 347574910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 20.aes_control_fi.66042862401998554790854153073750103614813623509226273550789367880350078615008
    Line 144, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10001624598 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10001624598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 75.aes_control_fi.113798136461633600488494883046107746500617058116748023125150306728250268622190
    Line 135, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/75.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007436938 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007436938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 10.aes_core_fi.50757573069414170432336804618283648886338112550197740346265323095506045903177
    Line 138, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/10.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10029561283 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10029561283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 26.aes_core_fi.82112920016942552640404591617123748758769252963892210054401049400339860986254
    Line 142, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/26.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002809543 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002809543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.105043235231402298082314287143505535250363496132016292396620462866819247937783
    Line 144, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 514008964 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 514008964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.26915415135210215726241646275705549146917623129969577869466456588332415361784
    Line 150, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 117799148 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 117799148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.114333742612119101114465671598458262759593942453046379649184313112168915531599
    Line 1000, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 709698565 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 709698565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 20.aes_core_fi.68881607056677431734540338019125844700716051733641901848829706986368445438084
    Line 138, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/20.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10026359298 ps: (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block.status.idle (addr=0x8e7d3384, Comparison=CompareOpEq, exp_data=0x0, call_count=10)
  UVM_INFO @ 10026359298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 29.aes_core_fi.22912300941638928625481725119367681195782522179295526487722799734607422519369
    Line 141, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/29.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10039705766 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10039705766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```