CSRNG Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: 06d697f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	143.953us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	3.000s	60.725us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	271.026us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	27.000s	2.209ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	12.000s	913.929us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	299.044us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	271.026us	20	20	100.00
		csrng_csr_aliasing	12.000s	913.929us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	15.000s	1.073ms	197	200	98.50
V2	alerts	csrng_alert	1.300m	4.955ms	500	500	100.00
V2	err	csrng_err	4.000s	93.672us	495	500	99.00
V2	cmds	csrng_cmds	6.867m	30.303ms	50	50	100.00
V2	life cycle	csrng_cmds	6.867m	30.303ms	50	50	100.00
V2	stress_all	csrng_stress_all	27.283m	130.709ms	45	50	90.00
V2	intr_test	csrng_intr_test	5.000s	233.715us	50	50	100.00
V2	alert_test	csrng_alert_test	5.000s	54.235us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	12.000s	924.216us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	12.000s	924.216us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	3.000s	60.725us	5	5	100.00
		csrng_csr_rw	5.000s	271.026us	20	20	100.00
		csrng_csr_aliasing	12.000s	913.929us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	226.590us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	3.000s	60.725us	5	5	100.00
		csrng_csr_rw	5.000s	271.026us	20	20	100.00
		csrng_csr_aliasing	12.000s	913.929us	5	5	100.00
		csrng_same_csr_outstanding	6.000s	226.590us	20	20	100.00
V2		TOTAL			1427	1440	99.10
V2S	tl_intg_err	csrng_sec_cm	8.000s	509.233us	5	5	100.00
		csrng_tl_intg_err	28.000s	2.047ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	4.000s	39.976us	50	50	100.00
		csrng_csr_rw	5.000s	271.026us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.300m	4.955ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	27.283m	130.709ms	45	50	90.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	15.000s	1.073ms	197	200	98.50
		csrng_err	4.000s	93.672us	495	500	99.00
		csrng_sec_cm	8.000s	509.233us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	15.000s	1.073ms	197	200	98.50
		csrng_err	4.000s	93.672us	495	500	99.00
		csrng_sec_cm	8.000s	509.233us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	15.000s	1.073ms	197	200	98.50
		csrng_err	4.000s	93.672us	495	500	99.00
		csrng_sec_cm	8.000s	509.233us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	15.000s	1.073ms	197	200	98.50
		csrng_err	4.000s	93.672us	495	500	99.00
		csrng_sec_cm	8.000s	509.233us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	15.000s	1.073ms	197	200	98.50
		csrng_err	4.000s	93.672us	495	500	99.00
		csrng_sec_cm	8.000s	509.233us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	15.000s	1.073ms	197	200	98.50
		csrng_err	4.000s	93.672us	495	500	99.00
		csrng_sec_cm	8.000s	509.233us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	15.000s	1.073ms	197	200	98.50
		csrng_err	4.000s	93.672us	495	500	99.00
		csrng_sec_cm	8.000s	509.233us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.300m	4.955ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	15.000s	1.073ms	197	200	98.50
		csrng_err	4.000s	93.672us	495	500	99.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	27.283m	130.709ms	45	50	90.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.300m	4.955ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	28.000s	2.047ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	15.000s	1.073ms	197	200	98.50
		csrng_err	4.000s	93.672us	495	500	99.00
		csrng_sec_cm	8.000s	509.233us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	15.000s	1.073ms	197	200	98.50
		csrng_err	4.000s	93.672us	495	500	99.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	15.000s	1.073ms	197	200	98.50
		csrng_err	4.000s	93.672us	495	500	99.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	15.000s	1.073ms	197	200	98.50
		csrng_err	4.000s	93.672us	495	500	99.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	15.000s	1.073ms	197	200	98.50
		csrng_err	4.000s	93.672us	495	500	99.00
		csrng_sec_cm	8.000s	509.233us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	15.000s	1.073ms	197	200	98.50
		csrng_err	4.000s	93.672us	495	500	99.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	7.667m	26.745ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			1617	1630	99.20

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.57	98.50	96.30	99.88	97.14	92.08	100.00	95.61	90.25

Failure Buckets

• xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed has 8 failures:
  • Test csrng_err has 5 failures.

    • 88.csrng_err.21576029678257910641935234789807673554759996527976699866899591534712402020521
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/88.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 3834243 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @   3834243 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   3834243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 90.csrng_err.89920775299682354760178445424450100603275471496410645612481633348752376189476
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/90.csrng_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 12163415 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @  12163415 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  12163415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.

  • Test csrng_intr has 3 failures.

    • 178.csrng_intr.19849152439388344951879183413820075893835272450792652672588575433229307151477
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/178.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 50214036 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @  50214036 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  50214036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 179.csrng_intr.67796871763145426927806626631427772307294720939704063323770268942397567936109
      Line 149, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/179.csrng_intr/latest/run.log

        xmsim: *E,ASRTST (/nightly/current_run/scratch/master/csrng-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,224): (time 136777293 PS) Assertion tb.dut.u_csrng_core.u_csrng_ctr_drbg_cmd.u_prim_fifo_sync_cmdreq.DataKnown_A has failed
        UVM_ERROR @ 136777293 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @ 136777293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 5 failures:
  • Test csrng_stress_all has 5 failures.

    • 15.csrng_stress_all.35527668834409425513093916897883601640223500218530740774291965165664069329558
      Line 154, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/15.csrng_stress_all/latest/run.log

        UVM_ERROR @ 2123395142 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 2123395142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 16.csrng_stress_all.5541501343206708501464196464320931452078319869554726134757890379041103071995
      Line 160, in log /nightly/current_run/scratch/master/csrng-sim-xcelium/16.csrng_stress_all/latest/run.log

        UVM_ERROR @ 5105831766 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 5105831766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 3 more failures.