EDN Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: 06d697f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.460s 20.321us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.270s 15.634us 5 5 100.00
V1 csr_rw edn_csr_rw 1.230s 12.185us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.510s 223.081us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.810s 62.548us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.370s 61.853us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.230s 12.185us 20 20 100.00
edn_csr_aliasing 1.810s 62.548us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 53.700s 2.422ms 300 300 100.00
V2 csrng_commands edn_genbits 53.700s 2.422ms 300 300 100.00
V2 genbits edn_genbits 53.700s 2.422ms 300 300 100.00
V2 interrupts edn_intr 1.450s 21.164us 50 50 100.00
V2 alerts edn_alert 1.830s 337.574us 200 200 100.00
V2 errs edn_err 1.800s 28.611us 100 100 100.00
V2 disable edn_disable 1.310s 11.466us 50 50 100.00
edn_disable_auto_req_mode 1.720s 41.767us 50 50 100.00
V2 stress_all edn_stress_all 6.320s 441.268us 50 50 100.00
V2 intr_test edn_intr_test 1.220s 15.709us 50 50 100.00
V2 alert_test edn_alert_test 1.390s 60.708us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.900s 133.267us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.900s 133.267us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.270s 15.634us 5 5 100.00
edn_csr_rw 1.230s 12.185us 20 20 100.00
edn_csr_aliasing 1.810s 62.548us 5 5 100.00
edn_same_csr_outstanding 1.660s 47.357us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.270s 15.634us 5 5 100.00
edn_csr_rw 1.230s 12.185us 20 20 100.00
edn_csr_aliasing 1.810s 62.548us 5 5 100.00
edn_same_csr_outstanding 1.660s 47.357us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 6.250s 6.297ms 5 5 100.00
edn_tl_intg_err 3.290s 103.116us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 0.890s 54.569us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.830s 337.574us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 6.250s 6.297ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 6.250s 6.297ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 6.250s 6.297ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 6.250s 6.297ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.830s 337.574us 200 200 100.00
edn_sec_cm 6.250s 6.297ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.830s 337.574us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.290s 103.116us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.850m 99.695ms 25 50 50.00
V3 TOTAL 25 50 50.00
TOTAL 1105 1130 97.79

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.52 98.87 94.23 97.02 91.86 96.33 97.56 92.75

Failure Buckets