ENTROPY_SRC/RNG_4BITS Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: 06d697f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 32.000s 32.823us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 89.603us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 3.000s 56.911us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 11.000s 955.418us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 5.000s 1.318ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 3.000s 61.699us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 3.000s 56.911us 20 20 100.00
entropy_src_csr_aliasing 5.000s 1.318ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 32.000s 32.823us 50 50 100.00
entropy_src_rng 9.067m 20.056ms 300 300 100.00
entropy_src_fw_ov 9.883m 18.026ms 292 300 97.33
V2 firmware_mode entropy_src_fw_ov 9.883m 18.026ms 292 300 97.33
V2 rng_mode entropy_src_rng 9.067m 20.056ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 16.867m 19.021ms 398 400 99.50
V2 health_checks entropy_src_rng 9.067m 20.056ms 300 300 100.00
V2 conditioning entropy_src_rng 9.067m 20.056ms 300 300 100.00
V2 interrupts entropy_src_rng 9.067m 20.056ms 300 300 100.00
entropy_src_intr 28.000s 523.342us 50 50 100.00
V2 alerts entropy_src_rng 9.067m 20.056ms 300 300 100.00
entropy_src_functional_alerts 7.000s 701.561us 50 50 100.00
V2 stress_all entropy_src_stress_all 8.200m 20.165ms 49 50 98.00
V2 functional_errors entropy_src_functional_errors 2.800m 10.016ms 996 1000 99.60
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 24.000s 336.011us 50 50 100.00
V2 intr_test entropy_src_intr_test 3.000s 34.135us 50 50 100.00
V2 alert_test entropy_src_alert_test 3.000s 139.646us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 183.781us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 183.781us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 89.603us 5 5 100.00
entropy_src_csr_rw 3.000s 56.911us 20 20 100.00
entropy_src_csr_aliasing 5.000s 1.318ms 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 120.171us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 89.603us 5 5 100.00
entropy_src_csr_rw 3.000s 56.911us 20 20 100.00
entropy_src_csr_aliasing 5.000s 1.318ms 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 120.171us 20 20 100.00
V2 TOTAL 2325 2340 99.36
V2S tl_intg_err entropy_src_sec_cm 3.000s 105.011us 5 5 100.00
entropy_src_tl_intg_err 4.000s 372.717us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 9.067m 20.056ms 300 300 100.00
entropy_src_cfg_regwen 3.000s 41.156us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 9.067m 20.056ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 9.067m 20.056ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 9.067m 20.056ms 300 300 100.00
entropy_src_fw_ov 9.883m 18.026ms 292 300 97.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 2.800m 10.016ms 996 1000 99.60
entropy_src_sec_cm 3.000s 105.011us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 2.800m 10.016ms 996 1000 99.60
entropy_src_sec_cm 3.000s 105.011us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 9.067m 20.056ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 2.800m 10.016ms 996 1000 99.60
entropy_src_sec_cm 3.000s 105.011us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 2.800m 10.016ms 996 1000 99.60
entropy_src_sec_cm 3.000s 105.011us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 2.800m 10.016ms 996 1000 99.60
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 7.000s 701.561us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 4.000s 372.717us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 9.267m 20.067ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 2555 2570 99.42

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
94.12 97.46 93.51 98.41 95.16 79.44 97.92 89.27 96.08

Failure Buckets