HMAC Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: 06d697f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	14.220s	5.729ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.100s	94.198us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.170s	36.277us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	12.970s	7.127ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.380s	1.156ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	14.033m	422.471ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.170s	36.277us	20	20	100.00
		hmac_csr_aliasing	8.380s	1.156ms	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.449m	5.067ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.422m	6.656ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.817m	91.992ms	30	30	100.00
		hmac_test_sha384_vectors	9.024m	252.864ms	75	75	100.00
		hmac_test_sha512_vectors	10.263m	66.338ms	75	75	100.00
		hmac_test_hmac256_vectors	16.750s	653.927us	50	50	100.00
		hmac_test_hmac384_vectors	18.330s	1.558ms	60	60	100.00
		hmac_test_hmac512_vectors	20.000s	408.235us	75	75	100.00
V2	burst_wr	hmac_burst_wr	50.160s	862.959us	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	25.211m	7.545ms	10	10	100.00
V2	error	hmac_error	1.604m	146.019ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	2.642m	57.141ms	10	10	100.00
V2	save_and_restore	hmac_smoke	14.220s	5.729ms	10	10	100.00
		hmac_long_msg	1.449m	5.067ms	10	10	100.00
		hmac_back_pressure	1.422m	6.656ms	25	25	100.00
		hmac_datapath_stress	25.211m	7.545ms	10	10	100.00
		hmac_burst_wr	50.160s	862.959us	50	50	100.00
		hmac_stress_all	50.893m	71.433ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	14.220s	5.729ms	10	10	100.00
		hmac_long_msg	1.449m	5.067ms	10	10	100.00
		hmac_back_pressure	1.422m	6.656ms	25	25	100.00
		hmac_datapath_stress	25.211m	7.545ms	10	10	100.00
		hmac_wipe_secret	2.642m	57.141ms	10	10	100.00
		hmac_test_sha256_vectors	4.817m	91.992ms	30	30	100.00
		hmac_test_sha384_vectors	9.024m	252.864ms	75	75	100.00
		hmac_test_sha512_vectors	10.263m	66.338ms	75	75	100.00
		hmac_test_hmac256_vectors	16.750s	653.927us	50	50	100.00
		hmac_test_hmac384_vectors	18.330s	1.558ms	60	60	100.00
		hmac_test_hmac512_vectors	20.000s	408.235us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	14.220s	5.729ms	10	10	100.00
		hmac_long_msg	1.449m	5.067ms	10	10	100.00
		hmac_back_pressure	1.422m	6.656ms	25	25	100.00
		hmac_datapath_stress	25.211m	7.545ms	10	10	100.00
		hmac_burst_wr	50.160s	862.959us	50	50	100.00
		hmac_error	1.604m	146.019ms	10	10	100.00
		hmac_wipe_secret	2.642m	57.141ms	10	10	100.00
		hmac_test_sha256_vectors	4.817m	91.992ms	30	30	100.00
		hmac_test_sha384_vectors	9.024m	252.864ms	75	75	100.00
		hmac_test_sha512_vectors	10.263m	66.338ms	75	75	100.00
		hmac_test_hmac256_vectors	16.750s	653.927us	50	50	100.00
		hmac_test_hmac384_vectors	18.330s	1.558ms	60	60	100.00
		hmac_test_hmac512_vectors	20.000s	408.235us	75	75	100.00
		hmac_stress_all	50.893m	71.433ms	50	50	100.00
V2	stress_all	hmac_stress_all	50.893m	71.433ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.980s	58.167us	50	50	100.00
V2	intr_test	hmac_intr_test	0.940s	14.252us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.060s	193.118us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.060s	193.118us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.100s	94.198us	5	5	100.00
		hmac_csr_rw	1.170s	36.277us	20	20	100.00
		hmac_csr_aliasing	8.380s	1.156ms	5	5	100.00
		hmac_same_csr_outstanding	2.720s	226.661us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.100s	94.198us	5	5	100.00
		hmac_csr_rw	1.170s	36.277us	20	20	100.00
		hmac_csr_aliasing	8.380s	1.156ms	5	5	100.00
		hmac_same_csr_outstanding	2.720s	226.661us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	1.450s	768.376us	5	5	100.00
		hmac_tl_intg_err	4.640s	135.626us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.640s	135.626us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	14.220s	5.729ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	9.170s	159.585us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	6.992m	3.582ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	4.510s	359.859us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.76	99.95	96.85	100.00	97.06	99.83	97.61	100.00