I2C Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: `06d697f`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.375m	8.031ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	41.770s	3.083ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.230s	43.403us	5	5	100.00
V1	csr_rw	i2c_csr_rw	1.130s	74.554us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	5.660s	549.875us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.290s	567.583us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.640s	32.354us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.130s	74.554us	20	20	100.00
		i2c_csr_aliasing	2.290s	567.583us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	7.590s	166.277us	4	50	8.00
V2	host_stress_all	i2c_host_stress_all	50.373m	28.218ms	12	50	24.00
V2	host_maxperf	i2c_host_perf	52.678m	31.443ms	49	50	98.00
V2	host_override	i2c_host_override	1.070s	96.675us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.540m	18.970ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.520m	19.566ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.900s	771.077us	50	50	100.00
		i2c_host_fifo_fmt_empty	23.200s	733.349us	50	50	100.00
		i2c_host_fifo_reset_rx	13.110s	997.185us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.596m	25.157ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	37.960s	951.740us	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	4.460s	492.955us	14	50	28.00
V2	target_glitch	i2c_target_glitch	2.810s	2.179ms	0	2	0.00
V2	target_stress_all	i2c_target_stress_all	34.252m	80.850ms	50	50	100.00
V2	target_maxperf	i2c_target_perf	9.510s	4.369ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.139m	1.765ms	50	50	100.00
		i2c_target_intr_smoke	11.450s	7.943ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.790s	261.523us	50	50	100.00
		i2c_target_fifo_reset_tx	2.680s	894.694us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	29.200m	73.083ms	50	50	100.00
		i2c_target_stress_rd	1.139m	1.765ms	50	50	100.00
		i2c_target_intr_stress_wr	6.341m	24.531ms	49	50	98.00
V2	target_timeout	i2c_target_timeout	10.440s	1.463ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	1.983m	4.284ms	48	50	96.00
V2	bad_address	i2c_target_bad_addr	9.590s	6.275ms	49	50	98.00
V2	target_mode_glitch	i2c_target_hrst	38.740s	10.184ms	26	50	52.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.890s	500.493us	50	50	100.00
		i2c_target_fifo_watermarks_tx	2.450s	205.697us	48	50	96.00
V2	host_mode_config_perf	i2c_host_perf	52.678m	31.443ms	49	50	98.00
		i2c_host_perf_precise	9.443m	24.251ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	37.960s	951.740us	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	11.120s	900.340us	49	50	98.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	4.050s	1.078ms	50	50	100.00
		i2c_target_nack_acqfull_addr	3.950s	4.193ms	50	50	100.00
		i2c_target_nack_txstretch	2.220s	492.969us	41	50	82.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	26.750s	667.649us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.530s	1.094ms	50	50	100.00
V2	alert_test	i2c_alert_test	1.000s	108.745us	50	50	100.00
V2	intr_test	i2c_intr_test	1.110s	19.072us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.780s	136.740us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.780s	136.740us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.230s	43.403us	5	5	100.00
		i2c_csr_rw	1.130s	74.554us	20	20	100.00
		i2c_csr_aliasing	2.290s	567.583us	5	5	100.00
		i2c_same_csr_outstanding	1.570s	156.497us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.230s	43.403us	5	5	100.00
		i2c_csr_rw	1.130s	74.554us	20	20	100.00
		i2c_csr_aliasing	2.290s	567.583us	5	5	100.00
		i2c_same_csr_outstanding	1.570s	156.497us	20	20	100.00
V2		TOTAL			1629	1792	90.90
V2S	tl_intg_err	i2c_tl_intg_err	2.740s	980.778us	20	20	100.00
		i2c_sec_cm	1.420s	79.854us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.740s	980.778us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	29.980s	1.316ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.020s	1.086ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	32.510s	1.010ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1809	2042	88.59

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
84.00	97.25	89.18	74.17	47.62	93.83	96.41	89.53

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 88 failures:

Test i2c_host_error_intr has 46 failures.

0.i2c_host_error_intr.30570590796896660437293039845104820734137504421965964934885736180632035608846
Line 123, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @ 166276677 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 166276677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_error_intr.28144850743431029328747823094787415305140602254591121852135353434067918906746
Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  15696108 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  15696108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 44 more failures.

Test i2c_host_stress_all has 28 failures.

0.i2c_host_stress_all.29961412491507627583077053271578525713625529613436833048665043001262710626689
Line 211, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 77715427397 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 77715427397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all.20166971949099272026898926244098651849260947764061111144736905287367450336700
Line 129, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 272333131 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 272333131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 26 more failures.

Test i2c_target_stress_all_with_rand_reset has 3 failures.

3.i2c_target_stress_all_with_rand_reset.84304820894044965837290482182869659863925099081076006935126794097345067401576
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @   8414536 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @   8414536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.i2c_target_stress_all_with_rand_reset.92107157418432763959563232666182295495214034508861987101502204969816047944674
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  36999093 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  36999093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test i2c_host_mode_toggle has 11 failures.

6.i2c_host_mode_toggle.20975057846982704930451619147389390109987953958571630513878261571346233542637
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  70491700 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  70491700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.i2c_host_mode_toggle.87377694726736549104531978551495324589846408292857733290624129392415620715995
Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/12.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  29410700 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  29410700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 24 failures:
- Test i2c_target_hrst has 24 failures.
  - 0.i2c_target_hrst.100554661922505687656355499729939366443957506509012214691080808854447450370758
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10059112148 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10059112148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_hrst.112728644941411994970809691855821106850972968670072179552770747065642036999367
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10416978410 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10416978410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 22 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 22 failures:
- Test i2c_target_unexp_stop has 22 failures.
  - 0.i2c_target_unexp_stop.64622314095964226173136480480737245922893473608957372441840117176282128241339
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 288942248 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 233 [0xe9])
  UVM_INFO @ 288942248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_unexp_stop.22083567283881530815117201991011439600964461238206020079660215741832034413569
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 205391133 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 17 [0x11])
  UVM_INFO @ 205391133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 20 more failures.

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 18 failures:

Test i2c_host_mode_toggle has 10 failures.

1.i2c_host_mode_toggle.36834430831126219774037994718114478940900714981555683359621468776586315775837
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 755815965 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @46562

10.i2c_host_mode_toggle.13381044927618478671280872124850933733485901053031228052577660392083756103348
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/10.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 502180379 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @67658

... and 8 more failures.

Test i2c_host_stress_all has 8 failures.

3.i2c_host_stress_all.63215402607042767642518800616543448458756960774374530474155912255907148121509
Line 122, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 34633388800 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1296075

7.i2c_host_stress_all.10351702978863516678930693209757780609135790766104108329599219975525929142906
Line 182, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 52631186399 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @4793831

... and 6 more failures.

UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.84396384171958018702276364954035016225843187130251204643133887651629862081590
Line 90, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 909537553 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 909537553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.15378484188875434116788154845008323026770720124904076387143463697438607541181
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 328329787 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 328329787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 6 failures.

0.i2c_target_stress_all_with_rand_reset.59550421354417172767581068206475749045433123716593482667768827078242088787777
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2781965882 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2781965882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all_with_rand_reset.48896925510558522787135266096275341846453288923114387311554960747273037948130
Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 861640598 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 861640598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 14 failures:

Test i2c_target_unexp_stop has 14 failures.

1.i2c_target_unexp_stop.50556115396092957981783040646283292635255302258835677737519616565790082175867
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 610890934 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 610890934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_unexp_stop.9637100909876167428107045785365798502150009068764000731554486944886400060351
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 231278142 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 231278142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 14 failures:
- Test i2c_target_unexp_stop has 14 failures.
  - 7.i2c_target_unexp_stop.43908766138846147287558380301633763629208444536841339050234659585821001063352
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/7.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 108533067 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 108533067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.i2c_target_unexp_stop.14588650130853084439356537229250175261282087900947286403525113560910670884190
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/8.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  66155701 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  66155701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 10 failures:

Test i2c_host_mode_toggle has 10 failures.

2.i2c_host_mode_toggle.43039025111250430511629019377818819517837848654786092274428541663260607210686
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  23947615 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

3.i2c_host_mode_toggle.99326239000329990113981575507984839969880790448826716680528395549574633898198
Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  49041396 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 8 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 9 failures:
- Test i2c_target_nack_txstretch has 9 failures.
  - 4.i2c_target_nack_txstretch.47392622205723225683656158777340246772421560518204444915644724187810771296800
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 475460465 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 475460465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 20.i2c_target_nack_txstretch.95468066650095685696302377131563882127289371414432359149340586966425006005150
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/20.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 283404450 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 283404450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 5 failures:
- Test i2c_host_mode_toggle has 5 failures.
  - 4.i2c_host_mode_toggle.14819718620660554656884814444879890626446918159749259884531948194266178362315
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  31104934 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0x52398a14, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  31104934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 16.i2c_host_mode_toggle.20221798247981607063776875586553483662431526374754484203018404639492176427113
    Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/16.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  62215490 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xa4950e94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  62215490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
Job timed out after * minutes has 3 failures:
- Test i2c_host_stress_all has 2 failures.
  - 2.i2c_host_stress_all.75616358639148493065073567140745825148384540710490573879750578646336790306703
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/2.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 23.i2c_host_stress_all.28300010611485084543035459534087297053336400238637320108651003330566294939776
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/23.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
- Test i2c_host_perf has 1 failures.
  - 5.i2c_host_perf.77733899742946530401134354108091416727780942134803393233090698407065410855705
    Log /nightly/current_run/scratch/master/i2c-sim-vcs/5.i2c_host_perf/latest/run.log
```
  Job timed out after 60 minutes
```
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
- Test i2c_target_fifo_watermarks_tx has 2 failures.
  - 9.i2c_target_fifo_watermarks_tx.24012213050356660921253283248682366138291796129843305853172723800262521769203
    Line 118, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 10.i2c_target_fifo_watermarks_tx.76747990519110674414357608678241203005096802682755159343031091767606886344924
    Line 118, in log /nightly/current_run/scratch/master/i2c-sim-vcs/10.i2c_target_fifo_watermarks_tx/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
- Test i2c_target_tx_stretch_ctrl has 1 failures.
  - 37.i2c_target_tx_stretch_ctrl.76960328924802574236513309029606702162470003242070420473152403404177812465026
    Line 127, in log /nightly/current_run/scratch/master/i2c-sim-vcs/37.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:

Test i2c_target_glitch has 2 failures.

0.i2c_target_glitch.60434226712593441361920530570879731729705369111807362030202366359634518959843
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 2179003676 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 2179003676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_glitch.20908661496541668751549137537589319656308301402479992002473304315114011646085
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log

  UVM_ERROR @ 446528507 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 446528507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 2 failures:
- Test i2c_target_stretch has 2 failures.
  - 3.i2c_target_stretch.6895426565366617626996598107719595210081808337519648329622177196835781919016
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/3.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10047597123 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10047597123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 41.i2c_target_stretch.93731555421771018156285748958014022359640837243683921145799188771796371541823
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/41.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10002243212 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10002243212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1142) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 4.i2c_target_stress_all_with_rand_reset.96236819949159487955928595767661186864166608925530685329190283117003364080727
    Line 102, in log /nightly/current_run/scratch/master/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 914485459 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 914485459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
- Test i2c_target_intr_stress_wr has 1 failures.
  - 9.i2c_target_intr_stress_wr.62894952514217645980666708178321050419144612321224088673088578814683221701704
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/9.i2c_target_intr_stress_wr/latest/run.log
```
  UVM_FATAL @ 51910078423 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 51910078423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_target_bad_addr has 1 failures.
  - 29.i2c_target_bad_addr.31121071983992904464897689257970089169328232191732797406710257317300558755974
    Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/29.i2c_target_bad_addr/latest/run.log
```
  UVM_FATAL @ 20000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 20000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 20000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```