KEYMGR Simulation Results

Sunday October 26 2025 00:06:53 UTC

GitHub Revision: `06d697f`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	25.350s	4.975ms	50	50	100.00
V1	random	keymgr_random	44.820s	2.448ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.440s	155.147us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.490s	31.585us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	23.410s	1.703ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	10.670s	1.815ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.160s	119.038us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.490s	31.585us	20	20	100.00
		keymgr_csr_aliasing	10.670s	1.815ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.283m	2.068ms	50	50	100.00
V2	sideload	keymgr_sideload	28.720s	11.562ms	49	50	98.00
		keymgr_sideload_kmac	43.130s	9.941ms	50	50	100.00
		keymgr_sideload_aes	23.950s	2.625ms	50	50	100.00
		keymgr_sideload_otbn	50.360s	8.073ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	18.130s	1.810ms	49	50	98.00
V2	lc_disable	keymgr_lc_disable	8.340s	1.254ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	6.980s	297.566us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	38.250s	1.791ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	41.510s	1.952ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	10.450s	615.038us	48	50	96.00
V2	stress_all	keymgr_stress_all	4.853m	15.405ms	48	50	96.00
V2	intr_test	keymgr_intr_test	1.010s	61.656us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.330s	105.845us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.760s	319.719us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.760s	319.719us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.440s	155.147us	5	5	100.00
		keymgr_csr_rw	1.490s	31.585us	20	20	100.00
		keymgr_csr_aliasing	10.670s	1.815ms	5	5	100.00
		keymgr_same_csr_outstanding	3.430s	448.454us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.440s	155.147us	5	5	100.00
		keymgr_csr_rw	1.490s	31.585us	20	20	100.00
		keymgr_csr_aliasing	10.670s	1.815ms	5	5	100.00
		keymgr_same_csr_outstanding	3.430s	448.454us	20	20	100.00
V2		TOTAL			734	740	99.19
V2S	sec_cm_additional_check	keymgr_sec_cm	9.870s	1.314ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	9.870s	1.314ms	5	5	100.00
		keymgr_tl_intg_err	7.590s	726.103us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.830s	238.457us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.830s	238.457us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.830s	238.457us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.830s	238.457us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	12.740s	2.061ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	9.870s	1.314ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	9.870s	1.314ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.590s	726.103us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.830s	238.457us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.283m	2.068ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	44.820s	2.448ms	50	50	100.00
		keymgr_csr_rw	1.490s	31.585us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	44.820s	2.448ms	50	50	100.00
		keymgr_csr_rw	1.490s	31.585us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	44.820s	2.448ms	50	50	100.00
		keymgr_csr_rw	1.490s	31.585us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	8.340s	1.254ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	41.510s	1.952ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	41.510s	1.952ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	44.820s	2.448ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	17.390s	4.014ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	9.870s	1.314ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	9.870s	1.314ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	9.870s	1.314ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	22.460s	2.223ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	8.340s	1.254ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	9.870s	1.314ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	9.870s	1.314ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	9.870s	1.314ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	22.460s	2.223ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	22.460s	2.223ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	9.870s	1.314ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	22.460s	2.223ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	9.870s	1.314ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	22.460s	2.223ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	19.260s	5.348ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1082	1110	97.48

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.64	99.13	98.15	98.19	100.00	99.01	97.71	91.26

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
- Test keymgr_stress_all_with_rand_reset has 21 failures.
  - 1.keymgr_stress_all_with_rand_reset.13327511042037213226146268806034069086424642454631415151788274996523073281839
    Line 468, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 609898611 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 609898611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.keymgr_stress_all_with_rand_reset.106534607057629919094215855862037532207990785430190406484283870402262210299102
    Line 188, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 122662776 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 122662776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 19 more failures.
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 11.keymgr_sync_async_fault_cross.96147166238662178617286595739967563390164775727278414665197585438257716167692
    Line 112, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @   5757914 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   5757914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sideload has 1 failures.
  - 27.keymgr_sideload.40640629814370062332740176249329405901825976963946239194978447265853044029087
    Line 117, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/27.keymgr_sideload/latest/run.log
```
  UVM_ERROR @   4844792 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   4844792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_direct_to_disabled has 1 failures.
  - 28.keymgr_direct_to_disabled.62566819192755702664635408565381742783048948547310461778894083354724401123503
    Line 211, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/28.keymgr_direct_to_disabled/latest/run.log
```
  UVM_ERROR @   7905492 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   7905492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 2 failures:

Test keymgr_stress_all has 2 failures.

14.keymgr_stress_all.44646217698100961713240557738187597589242568249925262687710088289039316031924
Line 703, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/14.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 675587899 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_0
  UVM_INFO @ 675587899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

46.keymgr_stress_all.26296389077802650832083275327295423150534393243374418223174821224897550454472
Line 106, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/46.keymgr_stress_all/latest/run.log

  UVM_ERROR @  19761065 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_1
  UVM_INFO @  19761065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:1142) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 11.keymgr_stress_all_with_rand_reset.3887432178393248442748246859476609444192103341904560242646690969991884225732
    Line 1804, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 555470317 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 555470317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err is not received! has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 29.keymgr_sync_async_fault_cross.73694219339882554333602908643209467744800617623442500634688457649425603144920
    Line 182, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  48539735 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err is not received!
  UVM_INFO @  48539735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```